San Jose, Calif. - Plunging yields, expensive packages and fab overcapacity are among the problems that could derail the move to sub-100-nanometer ICs, according to speakers at last week's International Symposium on the Quality of Electronic Design (ISQED) here. But presenters from industry and academia proffered a wealth of new ideas to cope with these issues.
Now in its fourth year, the IEEE-sponsored ISQED examines chip design methodologies, tools and manufacturing in an attempt to raise the bar on the quality of IC designs. This year's conference offered a robust technical program with nearly 100 papers and presentations, but suffered a 40 percent attendance drop, to roughly 150, because of international travel restrictions stemming from the war in Iraq.
A panel on the first day offered a stark warning: Yields for ICs with geometries below 100 nm may not exceed 50 or 60 percent. Panelists said that next-generation design flows will require an extraordinary degree of coordination among system-on-chip designers, CAD and IT departments, foundries and fabrication facilities, and third-party intellectual-property suppliers.
The separation between design and manufacturing only works through 0.13-micron geometries, said John Kibarian, president and chief executive officer of PDF Solutions. And even here, he said, yields are in the 50 to 70 percent range, and measures of quality like "contact failures per billion" are on the level of "one or two."
At 90-nm geometries, Kibarian said, the contact failures per billion must be some fraction less than one, just to maintain the same limited yields. This won't happen, he asserted, without some sort of design-for-manufacturing routine embedded in the design flow.
At a subsequent plenary session, Susumu Kohyama, executive vice president of Toshiba Semiconductor Co., described how his company is creating a standard methodology from design through manufacturing in order to ensure predictable yields. It's an attempt to cope with a number of challenges that Kohyama identified, including unstable Spice parameters, unpredictable interconnect, signal integrity problems and optical-proximity control issues.
If getting high-yielding dice isn't enough of a challenge, getting them into affordable packages could be even tougher. Panelists at another ISQED discussion emphasized the need for "IC/package co-design," but lamented the lack of automated tools that can help.
The need for co-design is driven by the emergence of advanced packages, such as flip-chip ball grid arrays with more than 2,000 pins, four or more layers, and I/Os in the gigahertz range. Such packages could jeopardize Moore's Law, said C.Y. Ho, vice president of engineering at Synopsys Inc. "I can see a scenario where you'd have a $10 chip in a $50 package," he said.
What's clearly needed, panelists said, is an ability to co-design chips and packages such that packaging trade-offs can be evaluated early in the design. However, for now, the reality is that packaging designers work alone, using little more than Excel spreadsheets to make their decisions.
Mike Hundt, director of corporate packaging for STMicroelectronics in North America, spoke of the advanced packages his company is using-including stacked packages, in which three or four dice are placed on top of one another. But the design of such packages is "all done by the seat of the pants today," Hundt said. "It's done with spreadsheets and some in-house expertise."
EDA vendor representatives acknowledged the problem but offered only limited help. Synopsys' Ho said there's a need for a concurrent die-and-package planning capability, comprehensive device verification, a vendor-neutral package database, and unified die-and-package modeling and simulation.
Existing EDA tools at least partially address many packaging concerns, but true co-design remains an elusive goal, said Lou Scheffer, a fellow at Cadence Design Systems Inc. "The problem is hard and the market is small, so you're not going to get an automated tool in this area," he said.
Leakage current poses another potential roadblock to sub-100-nm designs. That point was brought home in a plenary-session speech by Shekhar Borkar, director of Intel Corp.'s Circuit Research Lab. In about four years, Borkar said, advanced design teams could potentially place a billion transistors on a die. If threshold voltages continue to scale down and gate tunneling currents continue to rise, he said, those billion transistors would produce 100 watts of leakage power.
An immediate issue, Borkar said, is gate dielectric material. If a suitable high-k material is not found, he warned, oxide-thickness scaling will have to slow down and quite possibly stop, ending voltage scaling. Even with that result, something will have to be done to keep subthreshold leakage from growing to more than half of total circuit power, he said.
Borkar described an experiment at Intel in which body bias was applied to individual circuits within a die under external control to manipulate threshold voltage. The researchers were able to bring 97 percent of the dice in the lot into the top speed bin, and to moderate leakage current, he said.
Among the most provocative ISQED presentations was the one from Rubicad president and chief executive officer Michael Reinhardt, who said that overcapacity, not the high cost of fabs, is the real problem facing the semiconductor industry today.
Reinhardt said that the announced 200-mm and 300-mm fabs would essentially double the world capacity for advanced processes. No combination of markets on the horizon is capable of absorbing that much capacity, he said. Reinhardt suggested an entirely different direction based on two emerging technologies: nanoimprint technology and offset printing.
Nanoimprint technology physically presses a pattern from a tool into a settable gel. Offset printing is already being used in some relatively noncritical processes, Reinhardt observed. Both of these technologies, he said, could be used to make feasible a production "minifab" low enough in cost and high enough in capacity to meet the needs of most fabless semiconductor companies.
- Stephan Ohr and Michael Santarini contributed to this story.http://www.eet.com