SAN JOSE, Calif. Imagine what would happen if Major League Baseball decided to shorten the distance between the pitchers' mound and home plate, then cut the number of spring training days by half.
It's safe to say that even the league's best sluggers would be lucky just to connect with the ball when regular season begins.
Engineers in the optical lithoghraphy business are going through a similar ordeal as they struggle to keep up with Moore's Law. The rule book keeps changing and there are fewer opportunities to practice their craft in preparation for volume manufacturing, according to Chris Progler, chief scientist for mask maker Photronics Inc.
When the chip industry moves to the 65-nanometer node, Progler estimates that manufacturers will need to bring onstream no less than nine different resolution enhancement techniques. These are designed to make lithography more efficient, but the job of sorting these optical extensions will be immense and should lengthen the time needed to get it right, he said.
"Given all these efficiencies and how smart the lithographers are, we're still talking about 1.5 to two times more learning cycles," Progler told an audience here at process technology conference held by Semico Research Corp.
In reality, the reverse is happening. After studying mask turns, published technical papers, tool shipments and actual design rule shrinks, Progler found that in each case the number is declining from one process technology to the next.
The troubling conclusion: The lithography industry isn't getting the practice it needs to deliver the tools needed for furture process technology nodes.
"We need to get more learning cycles in lithography going. The pump has to be primed," he said. "The reality is that the success of optical lithography comes from trial and error."
Progler suggested several paths the industry can take to kick start lithography learning cycles. One is to use more simulation to connect different functional blocks and capture variability in the lithography flow, though it's still unclear who would pay for this development.
Another is to combat rising mask costs by using less complex masks and fewer wafers during pre-production stages. A third way is to convince chip makers to be less guarded about their resolution enhancement methods and try to build a consensus on which techniques should be used, similar to how the industry is handling the move to next-generation lithography.