TOKYO Sony Corp. and its Sony Computer Entertainment Inc. (SCEI) unit on Monday (April 21) announced a $1.7 billion (¥200 billion) investment plan for 65-nm process technology on 300-mm wafers.
Sony hopes the fab plan will allow it to develop process techology targeted for the "Cell" processor being developed jointly by IBM Corp., Sony and Toshiba Corp. since 2001 and embedded DRAM stemming from a joint research project with Toshiba.
SCEI also announced it has integrated the two key PlayStation 2 devices into one chip with 53.5 million transistors using a 90- nm process. Mass production using the 90-nm process will begin this spring, the unit said.
Sony's investment will be spread over three years to establish 65 nm process lines on 300 mm wafers with the total capacity of 13,000 wafers a month. This year, a clean room for a pilot line will be built in SCEI's existing Nagasaki fab 2.
Future spending plans and the location of new facilities have yet to be determined. Some portion of the investment will probably be used for Toshiba's 300-mm Oita fab.
Both the process shrink to 90 nm and the new investment plan for 65-nm technology means that Sony and Toshiba Corp. will fully integrate their processes for embedded DRAMs. Sony and Toshiba started joint process development in 2001 and completed a 90-nm process named CMOS4 in September 2002.
Toshiba started shipping engineering samples last September and mass production of devices for PlayStation 2 will start soon at Oita TS Semiconductor, a joint venture between SCEI and Toshiba, and this fall at SCEI's Nagasaki fab, in Isahaya City, Nagasaki Prefecture.
Joint development of the 65nm process called CMOS5 started last April and scheduled to be completed in two years. "We've agreed to continue the joint development towards the 45 nm CMOS6 process," said Ken Kutaragi, president and chief executive of SCEI. Kutaragi was promoted to executive deputy president of Sony main office on April 1.
Using the 90-nm CMOS4 process, SCEI integrated PlayStation 2 components into a single chip dubbedEE+GS@90nm. The device includes 53.5 million transistors and 4 Mbyte embedded DRAM in 86 square millimeter die size. It uses a 536-pin EBGA package. "With the practical product [EE+GS@90nm], we can launch mass production using 90-nm process smoothly," said Yoshihide Fujii, executive vice president of Toshiba Semiconductor Co.
With the shift to 90 nm, the embedded DRAM structure will change to a trench capacitor type from the stacked capacitor structure. Sony had collaborated with Fujitsu Ltd. to develop processes up to 0.18 micron and uses a stacked-capacitor DRAM for its embedded devices.
The integrated EE+GS@90nm device will be made at both OTSS and SCEI's Nagasaki fab using the same process.
The Cell microprocessor will be the main product at the new 300-mm wafer fab. The processor aims to provide tera-flops performance with low power consumption by using silicon-on-insulator wafers.
Cell has often been described as the next CPU for future versions of the PlayStation 2, but three Japanese companies intend to promote it for wider applications. One application is as a ubiquitous processor that can be used various broadband-network nodes. "It will be the processor that constitutes each server in networks," said Kutaragi.
Sony has its eye on top server vendor Intel Corp., which looms as a key competitor in the network sector. Kutaragi predicted bottlenecks in broadband networks would not be solved using existing PC technology. Hence, he said the Cell processor is designed to break that network bottleneck.
Sony's investment will beneficial not only to SCEI but to whole Sony group, said Kunitake Ando, president and Sony Group COO. Ando said Sony is buying nearly $8.4 billion worth of ICs annually.
"Less than 20 percent of them are internally produced. We purchased even core devices that differentiate products. If such devices are fabricated internally and the percentage of internally procured devices goes up twice, Sony's semiconductor strategy will change greatly," said Ando.