Each time the semiconductor industry stumbles, a chorus of doomsayers declares that the years of growth are over. I don't think so. While the industry has become large enough that its growth rate may slow, I do not foresee any long-term downturn. On the contrary, the industry is staged for significant growth in the 130- and 90-nanometer nodes. The move to those nodes, however, is being slowed by manufacturability and yield challenges that must be overcome.
Since the birth of the semiconductor industry, smaller features have characterized each new technology generation. Smaller features drove integration, and integration improved functionality, decreased cost and produced faster chips. This virtuous deflationary spiral made possible what we now take for granted-cell phones in restaurants and access to e-mail on vacation-for good or bad.
Beginning at the 130-nm node, this virtuous spiral showed signs of strain. Signal integrity, power, resolution enhancement and planarization issues, once relegated to the background, now take center stage and usher in a new world of manufacturability verification and analysis, sometimes called design-for-manufacturability.
For a viable semiconductor industry to exist at the 90-nm and 65-nm nodes, EDA tools must allow designers to consider and optimize for manufacturing at each step of the design, verification and tapeout process.
Synthesis, place and route, cell design and physical verification all need to automatically address a wide range of issues, while giving guidance on trade-offs in cases where automatic solutions are not possible. Physical verification and analysis will play a crucial role as the common ground between the designers and the manufacturing community.
Physical verification has already hit one wave of change due to manufacturability issues, with the second in progress. The first wave took physical verification from a simple yes/no design rule check to the level of dealing with challenges like planarization, antenna issues and optical process correction that result in radical changes to design data. In the future, physical-verification and analysis tools must allow for further optimization (operations like redundant vias), and let the user see where the inability to do so will have an impact on yield. This gives the ability to optimally trade off size and yield.
Manufacturability is going to define the progress of EDA over the next five years as surely as timing closure and database hierarchy did in the past five. With this work, we will establish a foundation for great success and a vital semiconductor industry. Without it, we'll have some explaining to do.