At the intersection of incredible technological progress and dramatic economic pressures, we find what I call the "techonomics" of IC design driving rapid changes in the relationship between electronic design automation and its users.
When it costs $200 million to $400 million to revamp a fab and roll out each new technology node, it's important to ask whether there is a sufficient corresponding investment to guarantee a solid pipeline of new designs to fill that fab. To be ready in time, semiconductor companies are developing close partnerships with EDA suppliers who offer a full platform of integrated tools to get the right mix of innovation, risk and cost. A strong working relationship with an EDA partner will result in a complete design flow that is tuned to the semiconductor vendor's technology and is capable of evolving quickly. Instead of gluing together a hodgepodge of niche tools that often result in a subpar solution, an integrated solution from a full-line supplier radically reduces risk. Furthermore, consolidating the number of suppliers into fewer-but closer-relationships will result over the long term in reduced costs.
Taken together, the key factors of technology innovation, risk and cost comprise the techonomics of design. Techonomics drives all major decisions in our industry today, including the adoption of new design tools and methodologies. Let's take the example of SystemVerilog, which got so much attention at this year's Design Automation Conference.
After 15 years of huge progress using Verilog and VHDL, in the last four or five years, verification has been rapidly running out of steam. As a result, we have witnessed the market introduction of a plethora of innovative ideas and tools, ranging from formal verification techniques to coverage metrics, to testbench creation tools, to assertion and property checking, to name a few. Many of these have been independently promising; in isolation, however, they have each lacked the ROI necessary to motivate designers toward widespread, systematic adoption.
With SystemVerilog, though, designers have found a language built on Verilog and a full understanding of the innovations from the last five years. Also, via mixed-language support from the main vendors, it can integrate legacy code in VHDL. One of the advantages of SystemVerilog is that it is 100 percent compatible with Verilog.
SystemVerilog is not the only current example of techonomics in action. Design for manufacturing, systematic reuse of intellectual property and hardware/software verification all illustrate the need to understand the intersection of technology evolution and economic realities. As we know, Moore's Law is a demanding mistress, and I predict that techonomics will drive tomorrow's semiconductor and EDA advances to meet those demands.