Tokyo - Semiconductor vendors that have placed bets on ferroelectric RAM are looking beyond standalone devices toward the day when the nonvolatile memory can be embedded in CMOS logic chips. That day stands on the other side of a considerable gulf of process and materials incompatibilities, according to developers, but bridges are rapidly spanning the chasm.
Matsushita Electric Industrial Co. Ltd. said last month that it had developed embedded ferroelectric RAM that is compatible with a CMOS process and does not deteriorate through multilayer interconnection processes. Taking advantage of FRAM characteristics, Matsushita intends to leapfrog competitors in volume production of system-on-chip (SoC) devices with embedded FRAM, starting with an 0.18-micron process this year.
Matsushita's first device with embedded FRAM was a simple 8-bit microcontroller with 64 kbits of FRAM and peripheral circuitry, designed for IC card applications.
"This is the first, practical result of our technology. We are going to offer larger-capacity embedded FRAM at a reasonable cost for other applications, such as cellular phones," said Susumu Koike, president of Matsushita Semiconductor Co. Matsushita, he said, intends to make the embedded FRAM business "one of its mainstays in the near future."
Built in 0.18-micron CMOS, the initial device operates on 1.1 volts. Sample shipments are to begin this month and volume production is scheduled for December at an initial capacity of 500,000 units a month.
FRAM has the advantages of nonvolatility, high-speed writing that's about 10 times faster than in flash memories and low power consumption. At the same time, certain disadvantages, such as difficult fabrication, big cell size, high cost and a high supply voltage, have held FRAM from a full takeoff.
Matsushita engineers focused on overcoming these disadvantages and finding a process to integrate FRAM with CMOS logic. "We have developed fundamental technologies that can be used when SoC LSIs shrink further in the future," said Koike. Matsushita's FRAM road map shows 0.13-micron embedded FRAM in 2005 and 90-nanometer devices in 2007 with reconfigurable processors.
The core of Matsushita's development is a hydrogen protection technology the company calls the fully encapsulated hydrogen barrier (FEHB). The process of forming multiple interconnection layers generates hydrogen, which deteriorates FRAM performance.
"For system-on-chip LSIs, multiple-layer interconnection of at least three to five layers is essential," said Kazuo Sato, councilor of the device group at the ULSI process technology development center of Matsushita. "The largest challenge was to protect FRAM from the effect of hydrogen."
Matsushita engineers encapsulated the whole ferroelectric capacitor-the strontium-bismuth tantalate layer and the electrodes sandwiching it-with a protection structure. The barrier protects the ferroelectric capacitor from hydrogen during multilayer interconnection processes. "As the barrier isolates the ferroelectric capacitor from other CMOS portions, the FRAM does not affect any CMOS parameters," said Sato. Thus, existing intellectual property can be used as is on the same chip as the FRAM, with no tuning.
Matsushita has developed a conventional FRAM cell that consists of two transistors and two capacitors in a planar layout. But the company's new embedded FRAM has one transistor and one capacitor in a stacked structure, copying a structure widely seen in DRAMs and utilized in some FRAM prototypes. "With the FEHB technology, the structure can be realized easily in FRAM," said Sato.
Existing FRAM implementations operate at 5 V to 3 V. But most SoCs presently operate at 1.8 V. Matsushita's conventional FRAM, with a capacitor that's 200 to 300 nm thick, operates at 3 V. But operating voltage can be lower if the layer is thinner.
Matsushita began joint FRAM development in 1996 with Symetrix Corp. (Colorado Springs, Colo.) based on the latter's strontium-bismuth tantalate material.
The lead-free SBT material has a structure known as layered perovskites, which consists of ferroelectric layers sandwiched by bismuth oxide layers. (A ferroelectric layer between two bismuth oxide layers measures about 5 nm thick.) The bismuth oxide layers protect the ferroelectric layer from deterioration, so Matsushita engineers reduced the thickness of the capacitor to 100 nm and lowered the operating voltage to 1.1 V.
Despite FRAM's promise as a nonvolatile memory contender, other next-generation nonvolatile memories are emerging, such as magnetoresistive RAM and ovonic unified memory. Each could play a niche role, Matsushita's Koike said. "Various memories will be used respectively in the most suitable applications. MRAM will have a big potential for storage applications. But FRAM has a strong affinity with CMOS processes, which makes it the most suitable for embedded use," he said.
Matsushita is now fabricating about 3 million units of FRAM per month on a 0.6-micron process. With the addition of 0.35-micron and 0.13-micron products, it aims to establish a production capacity of 10 million units per month in a few years.
On the materials front, FRAMs are roughly divided into two groups: SBT-based devices, using technology licensed from Symetrix, and thin lead zirconate titanate (PZT)-based varieties, using technology licensed from Ramtron International Corp. Texas Instruments Inc., with a license from Ramtron, developed a prototype last November that integrated a processor, peripherals and 64 Mbits of FRAM, produced in a 0.13-micron CMOS process. The company positioned the embedded FRAM as a next-generation nonvolatile memory technology, touting its low cost, high density and low power. TI plans to deliver a demonstration 3G single-chip radio with embedded FRAM next year, and plans to show 90-nm embedded FRAM devices in 2005-well ahead of Matsushita, which won't have 90-nm FRAMs until 2007.
Ramtron (Colorado Springs) itself plans to launch a line of embedded FRAM products later this year, enabled by a migration from 0.5- to 0.35-micron process technology. The company cites FRAM's 180-nanosecond write speeds, compared with 1 second for flash and 3 ms for E2PROM, and unlimited write access. Internal write voltage is 5/3.3 V for FRAM vs. 12 V for flash and 20 V for E2PROM.
"What we're beginning to do is integrate into a memory solution system-level components-primarily mixed-signal or specialized digital functions, but not a processor-to make something more application-specific," said Mike Alwais, vice president of FRAM at Ramtron.
Oki Electric Industry Co. Ltd. began joint development of embedded FRAM with Symetrix last February. It is using the same ferroelectric material as Matsushita, but is employing a nondestructive readout-cell structure. This will theoretically eliminate the limit on writing cycles. Oki intends to offer engineering samples fabricated on a 0.25-micron process early next year.
Fujitsu Ltd., a Ramtron partner and the sole volume supplier of PZT-based FRAMs at present, plans to begin fabricating SoC devices with embedded FRAM in an 0.18-micron process sometime in fiscal 2004. The company is now fabricating standalone FRAM on a 0.35-micron process.
To keep a lid on costs, Fujitsu manufactures embedded FRAM in fully depreciated fabs running 0.35- and 0.5-micron processes, said Tong-Swan Pang, FRAM marketing manager at Fujitsu Microelectronics America Inc. (Sunnyvale, Calif.). The existence of well-developed libraries and intellectual property helps reduce the risk for customers adopting the technology, Pang said. "We will move to 0.18 micron in the future, but how quickly will depend on how much money we can make at it," he said.
Toshiba Corp. and Infineon Technologies AG have been jointly developing PZT-type FRAM since 2001 and in February announced a 32-Mbit prototype built in a 0.2-micron process. Toshiba plans to offer engineering samples this month.