With system-on-chip design productivity partially resolved by using external intellectual property (IP) and improved EDA, design verification and test have emerged as the new SoC bottlenecks. Traditionally, test was purely a manufacturing responsibility. Today it is increasingly part of the SoC design.
SoC success is both a managerial and a technology issue, necessitating the use of reusable IP blocks from both internal and external sources. From a test point of view, these imported blocks are likely to come from a multitude of sources, each with its own test strategy.
Sheer complexity means that conventional functional test techniques are no longer sufficient. Newer designs use structural vectors where software deduces from the netlist how the chip should be internally structured. Automatic test pattern generation uses the software-derived test patterns to force transitions in every net, progressing now to built-in self-test, where extra circuitry generates its own pseudorandom test patterns, clocks the block and checks the results. Further complicating this issue is the fact that there is currently little reuse of test IP. A far better approach would be to have an international standard by which all IP is tested.
But as signals get faster, it becomes increasingly difficult to get signals from the chip to the tester, leading to the concept of logic or protocol analysis, with analog switches routing critical signals to those test blocks for measurement. Circuits will not only test the blocks but also switch off and replace arrays that have failed.
The Virtual Socket Interface Alliance working group on testability has proposed a series of standards for adapting a digital IP block to an SoC test methodology. The standard defines a "wrapper" to isolate the IP, and to respond to standard commands and connect to scan chains. A Common Test Language (CTL) is being created to help define the test structures and capabilities of a block. Chipless IP vendors then just deliver the IP with the associated CTL code.
With the classic chipless IP model now commoditized, tomorrow's chipless IC companies could well look to sell these IP test blocks.
Malcolm Penn is the chief executive officer of industry analyst Future Horizons (Sevenoaks, England; www.futurehorizons.com).