San Mateo, Calif. - A small company in Plano, Texas, has produced an unusual piece of synthesizable intellectual property that collects as many as nine 8051-compatible processors onto a single core. The processors can operate independently or as a single unit under the supervision of a lead CPU.
QuickCores IP's processor cluster is currently available for synthesis into Actel Corp.'s Axcelerator or ProASIC-plus FPGAs, but is portable to almost any synthesis environment, the company said. It can be used in a range of applications, from increasing the integration of a multicontroller system to implementing a cooperative multiprocessing architecture or fully fault-tolerant system.
The company began development of the processor cluster by trying to solve an altogether different problem, said QuickCores IP proprietor Jerry Harthcock: doing a completely hardware-based, noninvasive debug of an operating 8051 core implemented in an FPGA. Traditionally, debugging a small system is done by embedding a monitor program in the software.
However, this changes the software configuration and-critically, in real-time control applications-the system timing. It also means that a bug can crash the monitor along with the application, leaving the designer blind.
Alternatively, some processors embed the front end of a logic analyzer in the hardware, providing breakpoint registers and possibly a small trace buffer within the RTL. This is helpful, but still requires halting the CPU and executing debug code once an exception has been detected.External strength
Harthcock modified the 8051 core logic so that an external 8051 could, in effect, practice telepathy on the MCU core. The external device could have access to all of the target 8051's resources, and even fetch and decode an instruction, which the target would then execute. All of these activities were designed to be completely transparent to the normal operation of the 8051 core, so monitoring and debugging could proceed without changing the timing of the MCU running its application code.
Separately, Harthcock said, a customer became interested in integrating a number of the company's 8051 cores into a single FPGA. "These people use large numbers of radiation-resistant FPGAs in space applications," he said. While planning the best way to achieve high integration of multiple cores, it occurred to Harthcock that the debug hardware might have usefulness far beyond just debugging code.
Transparent access to a target MCU's resources, and the master's ability to cause the target to execute instructions, made for a powerful multiprocessing environment. Harthcock noted that the master MCU's transparent access into the targets permitted tightly coupled synchronization of multiple tasks on the target processors. It also permitted all the processors to be, in effect, ganged together to form a SIMD machine.
But for the space client in particular, the cluster had another capability. By using the ability of the master, or "bull processor," to look into the registers and memory of the target MCUs, it is possible to implement a tightly coupled redundant array for fault-tolerance. The bull can check the work of the other processors, or can compare them against each other. If a discrepancy is detected, the bull can correct the error, restart from a checkpoint or switch in another CPU.
It is even possible for one processor to run a task that checks for failures in the bull as the bull is checking everyone's work. Hence the MCU cluster may be a viable alternative to larger, code-incompatible processor cores or even to the development of custom hardware, the company says. The cluster can be implemented in off-the-shelf FPGAs and, potentially, in rad-hard parts.
The Pro8051 Hypercore is available in synthesizable Verilog. A development kit with a dual-processor core implemented in ProASIC-plus costs $499. A kit with a nine-processor version of the core implemented in an Axcelerator AX2000 sells for $3,000.