Santa Cruz, Calif. Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and verification. Available free online at www.cvsdl.com, CvSDL encompasses register-transfer-level (RTL) Verilog semantics and is being identified as a potential replacement for Verilog simulation.
Two-person Tenko Technologies was founded by CvSDL author Fukuji Sugie, the company's president. Within the next few months, Tenko will release a commercial version of CvSDL that works with Borland Software Corp.'s C++ Builder on Windows 2000 and XP, with an expected license fee of about $1,000.
Sugie hasn't worked for an EDA vendor but has been a development engineer, VLSI design engineer, firmware developer and project engineer. He got the idea for CvSDL when he was asked to look into the possibility of using C/C++ as a logic simulator. "I thought it would be great if we could design hardware just like software components," he said. "It appeared to me that [a C++ simulator] could benefit hardware engineers because it could be cheap and could be easily integrated into state-of-the-art software tools."
CvSDL is very different from the SystemC system-level language, Sugie noted. Aimed at RTL design, CvSDL handles asynchronous events and allows the same level of bit-level manipulation as Verilog. It also introduces the notion of components that use run-time port binding.
Perhaps most significant is its inclusion of "almost all" synthesizable Verilog-2001 features and most testbench features, Sugie said. CvSDL adds features similar to those in SystemVerilog, such as dynamic processes and buses. It does not include Verilog's switch-level features, and it leaves assertions for a later release.
"With CvSDL, the designer can still design as in Verilog while fully taking advantage of all C++ resources," Sugie said. "CvSDL is essentially Verilog; SystemC is not adequate for RTL design. There is very little risk in using CvSDL since the user continues to use Verilog, in slightly different syntax but in the same semantic way. Any design modules the user creates in CvSDL can be easily translated to Verilog."
Software designers can use CvSDL in hardware/software co-simulation environments to develop embedded operating systems and applications. They may also model device driver layers as CvSDL modules.
There are no CvSDL synthesis tools on the horizon, however, so CvSDL modules must be translated to Verilog or VHDL before synthesis. Tenko plans to provide CvSDL-to-Verilog and CvSDL-to-VHDL translators. The translation will require source code to follow certain coding styles.
Semantically, CvSDL provides synthesizable Verilog features including primitive gates and generated instances. What's not supported are switch-level constructs; user-defined primitives; "specify" block and timing check features; and, for now, signed logic types.
The commercial product will include a simulator to handle continuous and discrete time and event models. It will include an API to allow user control over the simulator, a waveform viewer and sample programs. Sugie said Tenko will continue to offer the free version of CvSDL, but it will be limited in capacity.
For now, Tenko is offering CvSDL free in hopes of lining up beta testers. An instruction manual and download of the library are available at the Tenko Web site.
Sugie said CvSDL can help overcome the hostility that RTL chip designers have expressed toward C-language design. "SystemC ignored some low-level but very important RTL design features. CvSDL solves that problem by providing Verilog compatibility. Designers can now take advantage of C++ resources and tools while retaining Verilog features."