Not every semiconductor company needs leading-edge technology. The analog/RF world has been quite happy with 0.35 micron and larger geometries for a number of applications. Analog does not scale like its digital counterpart, and therefore does not always benefit from the latest technology shrink. Unfortunately, most foundries are not interested in supporting specialty processes and have opted instead to aggressively ramp 0.18-micron and 0.13-micron digital CMOS processes with analog/RF modules included as an afterthought.
Fab renovations will definitely have an impact on analog/RF foundry business. Leading foundries prefer supporting companies that will consume thousands of wafers per month. To meet these quantities, it almost necessitates integration of as much logic, memory and analog/RF as possible. For leading-edge mobile applications, this might be a valid approach. But a typical analog/RF company uses hundreds to thousands of wafers per year for their applications. Will our future be based solely on system-on-chip (SoC) designs that require on-chip integration of analog/RF, digital and memory blocks? Realistically, most applications need hybrid approaches and, therefore, we will need foundries focused on best-in-class BiCMOS, SiGe and high-voltage processes.
How many companies are offering these foundry processes on cost-effective high-yielding 8-inch wafers, let alone provide accurate models that work in your design environment? Many foundries that claim the availability of these specialty processes are not prepared to support them with accurate models. What some of these foundries do have are fully depreciated 5-inch and 6-inch fabs with very aggressive wafer pricing. The big concern is process controllability that can impact die cost and delivery and actually can make it more expensive than using a higher value fab.
Some soothsayers challenge the notion that everything must be integrated into a single chip. Industry analysts claim that the majority of future SoC designs will have more than 50 percent memory content. So, if memory is the largest element of a SoC design and only requires three layers of metal for routing, why do we need to integrate all the memory with the rest of the digital logic that requires six to ten layers of interconnect? The most significant yield killer in deep-submicron designs is associated with the back-end metal process.
In addition, since memories push design rules aggressively, they will exhibit a higher defect density than standard logic. The price of standalone memory today is extremely low and the potential for embedded-memory yield loss can be significant. Along the same lines, do you need to integrate the analog/RF content, whose behavior can be highly influenced by switching noise from a high-gate-count digital chip? A multichip solution is a good idea if you have the board space, meet your performance targets, and your total bill of material (BOM) is less than the single-chip solution.
In addition, innovative packaging techniques such as stacked packaging or multichip modules may help you meet your cost points. Therefore, multichip solutions may be a better choice. Early proponents of single-chip 802.11x projects failed to deliver because of the limitations of the RF-CMOS process. Many switch-fabric and network-processing designs have elected to keep the serial-deserializer (serdes) and most memory off-chip due to power and cost challenges. If you have the board space, it's all right to use it.
However, if we do need multichip solutions, the challenge we will face is the availability of technologies to support our analog/RF requirements. The major foundries need to take advantage of higher profit margins to pay the large costs associated with today's wafer fabs (more than $4 billion for a 12-inch fab). These same foundries are not investing in the older technologies, and this is where the major challenge comes in. We still live in a world that often revolves around 5 volts. That pretty much precludes the use of 0.25 m and below.
When choosing an analog/RF foundry, don't just look for the availability of the selected processes, but also the corporate commitment to support the process. How well does the RF-Spice modeling match silicon? Does the foundry provide transistor matching data and 1/f parameters? Has the process been tested in Megahertz or Gigahertz? If you go to your typical digital foundry, you might get some parameters with support from the EDA community but not a whole lot of support to justify the results. It is not unheard of for analog/RF companies to use four to five multiproject wafers just to model a foundry's process. The dc values might look good but in the real world, ac values are critical. This additional qualification can kill your time to revenue and the viability of your company or at least your product line.
Modeling RF passives
A key differentiator is advanced RF simulation models for passive devices such as resistors, capacitors, varactors and inductors. The RF models should be part of the Spice model libraries, downloadable for a wide range of analog circuit simulators (e.g. Spectre, Agilent-ADS, ELDO, etc).
For RF circuits, the Spice model should be based on S parameter measurements up to frequencies of 40 GHz and higher. Besides the standard passive devices, special accumulation-mode MOS capacitors can be modeled as varactors. These devices are suitable for the design of high-performance voltage-controlled oscillators (VCOs).
Together with accurate RF models for active devices (MOS transistors, bipolar transistors) the RF passive device library enables realistic circuit simulation at high frequencies for both CMOS and BiCMOS applications.
All RF device libraries can be integrated into an RF process design kit for Cadence and Agilent ADS IC design systems. (Such design kits are offered by Austriamicrosystems to its foundry customers.)
A 0.35-micron CMOS process can serve the needs of RF circuits as well as wireline communications application-specific standard products. As a matter of fact, bipolar and BiCMOS circuits are far more sensitive to RFI than similar circuits in CMOS, because CMOS has no conducting diode path.
Austriamicrosystems' 0.35-m CMOS process family is fully compatible to the 0.35-m mixed-signal base process licensed from Taiwan Semiconductor Manufacturing Co. (Hsinchu City, Taiwan). The high-density CMOS standard-cell library optimized for synthesis and three- and four-layer routing guarantees highest gate densities. Peripheral cell libraries are available for 3.3 V and 5 V with high driving capabilities and excellent ESD performance. Qualified digital macro blocks (RAM, diffusion programmable ROM and DPRAM) are available on request. A variety of high-performance analog-to-digital and digital-to-analog converters can be provided for integration on the same ASIC.
Key features include:
0.35-m CMOS polycide-gate process; Four unrestricted layers of metal;
Second layer of poly for linear capacitors and linear resistors;
Peripheral cells with high driving capability;
High-performance digital and mixed-signal capabilities.
RF CMOS will supplement other mixed-signal processes-BiCMOS, SiGe or high-voltage processes-for analog/RF production.
Ron Vogel is business development manager at Austriamicrosytems AG, Premstatten, Austria and San Jose, Calif.