Many new portable applications call for higher levels of integration and low power, along with highly integrated digital and analog electronics, requiring low-power electronics to extend battery life and reduce device size. The most desirable process would offer high logic-gate density, high analog-component performance and buried layer isolation. It would also lend itself to system-on-chip integration.
Companies are meeting the demand with advanced process technologies that incorporate precision analog circuit components, such as a recently introduced analog CMOS process, HPA07. This 0.35-micron process was developed to support the analog design community, the primary objective being to integrate the highest performance standards in 1/f noise (often called that for its 1:1 inverse log dependency on frequency), matching, linearity and stability of both active and passive components. HPA07 is ideal for implementing products such as SAR converters, D/A converters, operational amplifiers, references, regulators, instrumentation amplifiers, delta-sigma converters and pipeline A/D converters. In addition, it is a good platform for integrating catalog products into an SoC with a moderate digital content.
HPA07 was developed and characterized in manufacturing to the tighter parametric tolerances demanded by higher precision analog designs. Similar process technologies usually center on the requirements of digital cores, and quite often the support of precision analog components is not adequate to meet the design and manufacturability requirements of the final product. The HPA07 process leverages existing logic fabrication and advanced CMOS processes to reduce cost and incorporate the analog needs. Such an application of existing resources allows the manufacture of precision analog-intensive CMOS circuits that offer component specs not generally available with other processes.
Along with high standards in noise, matching, linearity and stability, the HPA07 process provides cost containment and design flexibility through a large supported component base. The process incorporates up to 40 components with 20 mask levels (as opposed to the typical 20 components for the same number of mask levels). The node comes with two core voltage subnodes, 5.0-V 50HPA07 and 3.3-V 33HPA07. Each has been independently optimized for minimum 1/f noise and low-voltage MOS mismatch.
HPA07 is built on much of the same foundations as many of the available CMOS nodes. These include 8-inch wafer technology and 0.7-micron metal pitch. It also contains core components expected in analog CMOS technologies,such as:
- 12-V and 28-V breakdowns;
- high-voltage metal-insulator-metal capacitors;
- polysilicon medium- and low-value sheet resistors;
- npn and pnp bipolar-transistor implants or JFET implants;
- one-time-programmable EPROM;
- polysilicon fuses;
- IMD (metal plate) capacitors at 1fF/micron2; and
- buried-layer isolation.
In addition, there are four added capabilities less generally available:
- a high-precision titanium nitride (TiN)-polysilicon capacitor;
- a laser-trimmable silicon chromium (SiCr) 1-kohm/cm2 thin-film resistor;
- a thick copper final metal-routing layer; and
- a low-cost mid-density E2PROM.
MOSFET noise was reduced roughly two times from what is available in the industry. Low 1/f noise can be seen in the OPA300, which is the first op amp developed in the HPA07 process technology. It shows superior gain-bandwidth product and noise combination (180 MHz, 3 nV square root Hz).
Low-noise NMOS and PMOS transistors are important for improving the dynamic range of the op amps and the overall resolution of the data converter. Electronic designs are moving toward single-supply operation at 5 V, 3 V and lower, cutting cost and conserving power. But it takes a toll on available dynamic range, a valuable commodity in analog design. A key figure of merit for dynamic range is signal-to-noise ratio (S/N).
Noise comes in various forms. In an amplifier, noise is composed mainly of flicker noise (often called 1/f noise), thermal noise and shot noise. An A/D converter has these plus additional noise caused by the sampling process. Reduced supply voltage results in reduced signal levels. When noise remains constant, the result is a commensurate reduction in S/N, forcing the noise reduction needed in the basic MOS transistors.
Both the high-precision capacitor and precision thin film (SiCr) resistor use substantially new integrations made possible only with the advanced logic-derived tool set and fabrication process expertise. Overall, the program has met, if not exceeded, expectations across the key performance requirements.
See related chart |
Linear CMOS and implantable passives support high-precision amplifiers and data converters.
Source: Texas Instruments
To achieve the requirements for the high-precision capacitor, the HPA07 process development had to consider the importance of achieving a low voltage coefficient (VC), optimized matching, a low capacitor temperature coefficient (TC) and a reduced dielectric absorption (DA). The low VC was achieved by using metal plates and the proper dielectric and the matching by using the advanced 200-mm fabrication tool set. The reduced dielectric absorption was a function of optimized dielectrics and oxide treatments. The work resulted a 3-ppm/V VCL, 3-ppm/V2 VCQ, 5-ppm/ degrees C TC, 16-bit matching and 60-ppm DA.
These precision parameters are important in the development of high-accuracy SAR and delta-sigma converters. Their achievement has a direct impact on the A/D converter's linearity as well as the circuit area.
The integration of a best-in-class 1-kohm/cm2 SiCr thin-film resistor was mainly achieved by using the 200-mm single-wafer tool set that was available. With this equipment, 16-bit initial matching was achieved, which is 2 bits better than the typical industry result. The initial matching parameter allows for the same matching specification at one-fourth the area. Matching stability is improved by a factor of 2 (10 ppm vs. industry-typical 20 ppm).
Improvements were also made to the polysilicon resistor matching (12.2 ppm) and long-term transistor Vt stability (50 microvolts through life test).
William Boyd is manager of high-perfor-mance linear technology development at Texas Instruments Inc. (Dallas).