Today the market for high-speed analog ICs is growing rapidly because of the ever-increasing demand for bandwidth. High-bandwidth amplifiers are finding such applications as xDSL and cable modems, set-top boxes, contact image scanners, DVD players and CD-ROMs. For portable, battery-powered and USB applications, power consumption must be low. In many of these designs, single-supply operation at 5 or 3 volts is preferred. Fabrication processes such as National Semiconductor's VIP10 process are intended to serve these markets.
VIP10 is the latest member of National's Vertically Integrated PNP family of complementary bipolar processes. Complementary bipolar transistor designs, by using high-performance npn and pnp transistors, can offer the best combinations of features required in today's high-speed amplifiers: high bandwidth, low power consumption, low supply voltages, large output swing, high output current and low distortion. In March 2001, National launched its LMH (Linear Monolithic High-Speed) family of high-speed amplifiers designed on the VIP10 process.
Why complementary bipolar?
Just as complementary MOS (CMOS) processes incorporate NMOS and PMOS field-effect transistors, complementary bipolar (CB) processes incorporate npn and pnp bipolar-junction transistors. CMOS is ubiquitous today because CMOS logic gates dissipate no static power yet have high drive current and speed. Similarly, CB processes enable Class AB output stages with low quiescent current and high output drive in analog circuits.
Furthermore, CB processes permit high-swing complementary common-emitter output stages, commonly known as rail-to-rail outputs. On some processes, these output stages can be a challenge to design with well-controlled frequency- and time-domain responses because the output transistors vary from quiescent conditions to sinking or sourcing high currents to near saturation of the output transistors. Because of low collector resistance and reduced quasi-saturation effects, the VIP10 will make amplifiers with rail-to-rail output stages.
Low-supply operation is increasingly important, since many systems employing high-speed analog circuits use only a single supply voltage such as 5 V or 3 V. The minimum supply voltage for bipolar designs is a forward base-emitter voltage plus a saturation voltage, or approximately 1 V. A part such as National Semiconductor's LM10 op amp/reference operates down to a 1-V supply. But because the LM10 was fabricated on a junction-isolated process lacking a high- performance pnp, its gain-bandwidth product is a low 100 kHz. With VIP10, one could design an op amp with a 1-V minimum supply voltage and a gain-bandwidth product about 1,000 times greater.
Rail-to-rail input stages can be designed on a CB process by combining both pnp and npn input stages. Other circuitry is required to steer current to the appropriate differential pair depending on the common-mode voltage, and both stages usually require a folded-cascode-to-level-shift circuit. A CB process with high-performance bipolar junction transistors (BJTs) of both types will ensure a consistent performance stage when either input stage is active. A small device footprint reduces the die size required by this more complex circuit.
The goal of the VIP10 process development was to deliver the highest level of analog performance possible while minimizing wafer cost and development time. The performance benefits of CB analog ICs can be seen in the analog circuits used in wired broadband applications, such as xDSL and cable modems. The most critical analog blocks are the drivers and receivers. Receivers using low-base-resistance BJTs can offer low input-noise voltage with a much lower operating current and die area than CMOS designs, because of differences in device physics.
Line drivers must drive transmission-line loads to high power levels with low distortion. CB designs yield lower distortion than CMOS because of the higher transconductance of BJTs. Also, the high gate capacitance of large MOSFET devices would cause problems with stability or power dissipation. In practice, CB designs are superior in combining low distortion, low power dissipation and frequency stability. The higher breakdown voltages achievable in high-speed BJTs give the CB line driver higher output swing.
In CMOS, the key dimension is the minimum channel length, which determines the power-delay product and the IC area. Reducing MOS channel length is expensive since it is set primarily by lithography. The analogous parameter for bipolar transistors is the vertical dimension of the active base region (base width), critical for determining current gain and transition frequency. These junction profiles are controlled by implantation and rapid thermal annealing. Since the minimum feature size for a BJT (usually the emitter-stripe width) is less important than for CMOS, a high-performance CB process can be developed with less investment of capital and time. VIP10's minimum emitter width is 1 micron, allowing it to be manufacturable at a low cost.
Lower parasitics mean a higher speed/power ratio. VIP10's excellent transistor performance stems from its advanced process architecture. The active area is silicon-on-insulator, which is fabricated using the bonded-wafer technique. This produces a buried oxide layer that isolates the bottom of the epi tubs, which are usually the collectors of bipolar transistors. P- and n-type buried layers are followed by epi growth. Trenches are anisotropically etched into the silicon and filled to form the isolation sidewalls. Consequently, the VIP10 transistor collectors are fully dielectrically isolated (DI) and have no p-n junction between the collectors and substrate or well. Earlier processes were junction-isolated (JI) so that the BJT collector-substrate capacitance (Cjs) was primarily a junction capacitance. Since junction capacitance varies with voltage, this caused undesirable variations in ac performance since supply voltage and output voltage are varied and increased distortion.
Collector-substrate capacitance on a JI process is usually higher than on a DI process. High Cjs will either degrade amplifier frequency response or require increased quiescent current. The situation gets even worse for one transistor type on JI. National's VIP1, VIP2 and VIP3, like most bipolar processes, are fabricated on a p-type substrate wafer. To isolate the pnp transistor collectors from the substrate, an n-type buried isolation diffusion is employed. This n-type diffusion must be more highly doped than the p substrate. This highly doped junction causes the Cjs of the pnp to be much higher than that of the npn. On VIP10, thanks to its dielectric isolation, collector-substrate capacitance of the minimum devices is a very low 5 fF, independent of voltage and equal for both npn and pnp.
The next parasitic capacitance to address is the collector base or Cjc. When referred to the input of a voltage gain stage, this capacitance will increase because of the Miller effect. In high-speed transistors, a lightly doped intrinsic base is contacted by a highly doped extrinsic base diffusion. This extrinsic base region produces a large base sidewall capacitance. VIP10 eliminates this problem with dielectric isolation at the sidewalls. This is done with a shallow trench etch and fill.
Two polysilicon layers are used for emitter and base contacts. This permits the critical emitter and base regions to be self-aligned. A Poly 1 region defines the extrinsic base region. A hole inside the poly 1 geometry is the emitter window and intrinsic base. The emitter, which is separated from the extrinsic base by a nitride spacer, is contacted by the Poly 2, allowing the base pickup to be very close to the emitter, reducing the extrinsic base resistance. Both polysilicon layers are salicided, further reducing the parasitic resistances in series with emitter, base and collector.
The minimum VIP10 transistors have a very small 300 mm2 nt, one-eighth that of the previous generation-another benefit of the features just discussed. The double-poly architecture reduces spacing from the emitter to the base pickup. The shallow trench isolation on the base sidewalls allows the collector pickup to be very close to the base without decreasing the breakdown voltage or increasing the capacitance. Finally, the trench isolation around the device drastically shrinks the area required for isolation.
The most common ac figure of merit for a bipolar transistor is the transition frequency, or fT, which is the frequency at which the common-emitter current gain decreases to unity. The fT of the VIP10 npn and pnp at Vce = 5 V is 9 GHz and 8 GHz respectively, about 50 percent higher than on competitive processes. A high transistor fT means that its emitter-base diffusion capacitance will be low for a given operating point. With VIP10 transistors, National can design amplifiers either with bandwidths exceeding 1 GHz, or in the 100-MHz range with very low power consumption. This is because the internal stages will have low phase shifts even at very low operating currents, since both diffusion and parasitic capacitances have been greatly reduced.
High-speed transistors tend to have poor dc performance, but this is not true for VIP10. Beta and early voltage are 100 V and 120 V for the npn and 55 V and 40 V for the pnp. A common dc figure of merit is beta times early voltage, which is related to the gain obtainable from a single amplifier stage. The VIP10 pnp has a beta*Va product of 2,200 V, BVceo of 12 V and fT of 8 GHz, which is a world-class combination for a complementary bipolar linear IC process.
Low-current performance, sometimes a concern on high-speed processes, is not an issue on VIP10. Transistor beta is constant over more than four decades of collector current. Entire VIP10 op amps have been designed with supply currents below 10 mA.
Michael Maida is senior member of the technical staff, operational amplifier product group, at National Semiconductor Corp. (Santa Clara, Calif.).
See related chart