# Signal integrity key for Gbit interconnects

As modern signaling standards push digital designs to the gigahertz and gigabit ranges, interconnect performance becomes the key factor in enabling reliable system operation. Signal integrity issues such as reflections, crosstalk, frequency-dependent transmission-line loss and dispersion can significantly degrade system performance and reliability.

The ability to simulate and accurately predict the effect of these signal-integrity issues is critical to achieving a working design, and this ability is contingent on the designer's ability to obtain accurate interconnect models for each part of the interconnect link-from the driver chip, through the package into the daughtercard; through a high-speed backplane connector to the backplane, and to the cable interconnect between subsystems.

Deterministic jitter and eye-diagram degradation are caused by frequency-dependent losses and crosstalk in interconnects, and must be modeled using coupled and lossy transmission-line models. Signal distortion and digital switching errors result from crosstalk, reflections and ringing in interconnects. Modeling the crosstalk requires coupled line modeling techniques. Understanding reflection demands increased impedance measurement accuracy and transmission-line modeling. Signal ringing requires an understanding of interaction between the lumped (RLC) and distributed (transmission line) elements in the system.

The different pieces of the interconnect puzzle include backplane traces, that is, single-run or differential, on a single layer or different board layers; vias; connectors and connector-cable assemblies; IC packages and sockets. Electrically short structures, such as vias, packages and connectors, can be modeled using an RLC approach, whereas board traces and cables must be represented by distributed elements (transmission lines). For the backplane traces and cables that are long, we must include frequency-dependent losses in the transmission-line model in order to accurately predict propagation delay, jitter and eye-diagram degradation.

We can use a lumped model for the interconnect or interconnect segment if the interconnect propagation delay is much shorter than the rise time of the signal propagating through the interconnect.

It is imperative that the designer defines the range of validity of the model through the rise-time specification. This rise time is typically determined as the fast corner of the drivers to be used with a given signaling or I/O standard. A model that operates to a faster rise time than necessary will take much more time to extract and simulate without providing any benefits to the designer.

Once the accurate measurement-based model is extracted, it is important to validate the accuracy of the model by running simulations in the designer's simulator of choice and comparing them to the measurements.

The designer can analyze his or her interconnects, and extract the interconnect models using a number of prelayout analysis and electromagnetic-field-solver tools. However, comparing the model with real measurements is paramount.

Any impedance measurement errors caused by an effect known as "multiple reflections" can be corrected using an impedance-deconvolution algorithm. The designer can also use the impedance-profile-modeling approach to generate a Spice or I/O Buffer Information Specification signal-integrity model for the interconnect. The model generated using the impedance-profile approach based on time-domain reflectometry (TDR) measurements has the advantage of a one-to-one correlation to the physical geometry of the backplane or cable interconnects. Each transmission line corresponds to a backplane trace or a cable segment; each lumped element corresponds to a board via or a connector. Because all the modern standards are differential, all of this analysis must be performed in differential 4-port mode.

**Lossy line modeling**

Frequency-dependent transmission-line losses need to be modeled for longer segments of backplane traces and cables. Skin effect and dielectric loss are the two key components of the transmission-line losses, contributing to rise-time degradation and amplitude degradation in the signal. Rise-time degradation can cause significant difference in delay between the driver and a receiver, and amplitude degradation can completely prevent the receiver from switching. Both of these effects, combined with the crosstalk-related pattern-dependent jitter, may result in significant degradation of the eye diagram.

Even though a vector network analyzer (VNA) is the instrument that allows direct measurement of the frequency-dependent behavior of an interconnect, TDR measurements contain all the information about the frequency dependence of an interconnect.

Sometimes, it is difficult to distinguish losses from impedance variations when doing measurement-based analysis. In cases like this, you may need to use a behavioral modeling algorithm. Such an algorithm does not discriminate between losses and reflections, but instead creates a complete model for an interconnect directly based on the corresponding TDR or VNA measurements. This model will accurately predict both the time and frequency domain behavior of the interconnect.

The advantage of behavioral algorithms is that they can generate a model fully automatically, and can even automatically select an appropriate topology for the model. However, this selected topology does not necessarily match the expected physical topology for the DUT. When using a behavioral model, one would not be able, for example, to separate the model for the connector out of the bigger backplane model. Therefore, behavioral models are great for generating a quick model for the interconnect when a designer needs to include such a model in the simulation, but they are less useful when a designer is trying to find the causes of problems in his interconnect link.

Based on the techniques described above, it's possible to put together a complete methodology for modeling an interconnect link. The behavioral modeling algorithms can be applied when the designer needs to generate a quick model, or when a topological model is difficult to obtain. It's possible to combine the lossy line modeling with impedance profile-(Z-line) based modeling to generate an accurate topological model, and the Jedec-based RLC modeling can be used to model isolated lumped element components in the link.

To demonstrate this methodology, we applied it to a Gigabit Ethernet backplane populated with two daughtercards. First, we extracted the lossy line model for the daughtercard. Second, we extracted the daughtercard-to-backplane connector model using the impedance profile. Then, we extracted the lossy line model for the backplane. The simulations using this model were performed in HSpice and Berkeley Spice, and the resulting correlation is shown.

The eye diagram can be predicted based on these modeling results, or directly predicted based on TDT measurements.

*Dima Smolyansky is co-founder and product marketing manger at TDA Systems (Lake Oswego, Ore.).*