Historically, field-programmable gate arrays and printed-circuit boards have been conceived in disparate design environments. Toss the FPGA over the wall, and let the pc-board designer figure out how to meet the 10-nanosecond interconnect delay budget across a 300-pin ball grid array.
Today's largest FPGA devices employ more than 1,700 pins, up to a million gates, and offer functionality and flexibility that dwarfs technology from as recently as five years ago. Couple that with sub-nanosecond timing margins for signals transmitted at 300 MHz and higher and you've got the formula for some serious design headaches.
The only constant in FPGA design is the changes that occur along the way, both at the interconnect level to meet timing and loss requirements and with pin assignments within the FPGA itself. The great benefit of design flexibility offered by the FPGA is also one of the biggest nightmares for board designers.
The FPGA design flow uses a language-based approach, while the pc board uses a schematic-entry methodology. The language-based hardware description language (HDL) representation of the FPGA must be properly represented as a schematic symbol containing the pin assignment information, as well as the appropriate links to the layout tool. Eventually, these two design worlds must be synchronized through proper FPGA pin assignments on the circuit board, and represented in the schematic symbol and pc board footprint database--yet by different design teams, using completely different tool sets.
The FPGA designer must satisfy synthesis, as well as place-and-route constraints to meet FPGA timing specifications. On the other hand, the pc-board designer must constrain the design on the back-end to meet the system timing and signal-integrity requirements at the system level. It is increasingly common that these constraints conflict between the two parallel design flows. Unique to FPGA and pc-board implementation, this raises the need for concurrent, interactive design methodologies that provide the highest probability of creating a routable design, meeting signal integrity and timing requirements on the first pass.
A moderate-size FPGA (about 300,000 gates) should take about three months to develop. Once you've agreed on the pin-out, both logic and system design can commence. Recent research shows that the average printed-circuit-board design takes about three months, as well. Changes in circuit-board layout are not as easy as turning and burning a reasonably sized FPGA design revision (a couple of days). Therefore, it is reasonable to focus attention on the more painful design changes associated with pc-board interconnect design. It is reasonable to expect that four to five weeks can be pulled out of the board design schedule through process automation and using common sense.
Two classes of signals pose problems for FPGA designers and their downstream counterparts at the system level: timing-sensitive synchronous signals and asynchronous, multigigabit serial I/Os.
We've all heard the phrase "timing is everything," and this is certainly the case for most of the digital outputs on an FPGA. Though accountants may argue otherwise, timing is more important than manufacturing cost. If a design costs too much, profitability is reduced. On the other hand, if timing or signal qualities go awry, profitability is reduced to zero because the product won't function.
The FPGA team may place and route the FPGA itself according to their specific timing requirements. However, system-level timing issues must be negotiated between the board and FPGA teams. If the collaboration occurs too late in the design process, unnecessary schedule slides can result. With the subnanosecond timing margins associated with many signals, it's common for the system side to be faced with pc-board floorplanning changes, part rotation and the need to negotiate pin swaps with the FPGA team. For smaller FPGA designs, it's common to see five to 10 pin swaps during interconnect design and many more for today's large-scale FPGAs.
To make the interaction seamless it is advantageous to employ a tool that synchronizes the FPGA and board databases. It is also prudent to do as much pre-layout and "what-if" analysis to avoid weeks of spinning actual prototypes. Instead, digital representations of circuits can be developed in a matter of minutes.
Prelayout signal integrity and timing "what-if" analysis using an FPGA vendor's I/O Buffer Information Specification (Ibis) IC buffer models and a prelayout signal integrity simulator are good for making interconnect course corrections. For example, Xilinx Inc. (San Jose, Calif.) provides an Ibis writer as part of its free software. System engineers with tight timing budgets want to use pre-layout simulation to compensate for intellectual-property providers' clock-to-output timing values, allowing them to adjust to actual printed-circuit board interconnect loads rather than the test loads used to create data book total cost-of-ownership values. Ten percent timing calculation mistakes are tolerable at 20 MHz, but at 300 MHz and above, those are unacceptable.
Many FPGA manufacturers, including Xilinx, Altera Corp. (San Jose) and Lattice Semiconductor Corp. (Hillsboro, Ore.), are now supporting multigigabit serial transceiver technology aimed at narrowing data paths significantly while dramatically increasing throughput. Some system designers are projecting cost savings of up to 40 percent by moving from wide, parallel architectures to serial or serial/deserializer (serdes) implementations.
With the significant promise of multi-gigabit-per-second serial I/O, new design issues surface. Instead of worrying about system timing, over/undershoot crosstalk and proper termination, design attention must be focused on issues such as dielectric loss, skin effects, deterministic and random jitter and their effect on intersymbol interference, as well as percent eye opening. Eye diagrams are compared to eye-mask specifications associated with various multi-gigabit design standards such as PCI Express, Xaui, Serial ATA, HyperTransport or Infiniband.
Performing this analysis on multigigabit differential signals is relatively easy with a good understanding of the variables and the right tools. At multigigabit speeds, three primary factors contribute to signal degradation and attenuation in differential, multigigabit signals: dielectric loss (as a function of length and board material), vias and connector loss. Vias, depending on geometry, can contribute between 0.5 and 1 dB of loss per via, against total loss budgets that range from 10 to 15 dB, typically, for several of the newer serdes bus specifications.
For this reason, most FPGA manufacturers recommend that multigigabit transceivers be placed on the perimeter of the FPGA, to eliminate the need to drop vias down to internal signal layers. FPGA manufacturer specifications recommend careful stack-up planning for these signals to achieve carefully calibrated differential impedance. A rule of thumb in FPGA stackup design is to plan for a layer in the circuit board for each row of signals in the ball-grid array package, allowing plenty of room for drop-down vias between pins.
One thing that is can be measured is how long it takes for an FPGA to be integrated into a pc board and seeing where a schedule can be compressed. With the tools available for today's high-speed, high-gate-count and high-pin-count FPGAs, it makes no sense to brave this process without being armed with the right tools and collaborating closely between the parallel paths of FPGA and printed-circuit board design.
Bill Hargin is a product-marketing manager at Mentor Graphics Corp. (Wilsonville, Ore.)
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