In a modern high-speed bus, numerous subsystems make up the entire interconnect. These subsystems consist of the input/output buffers located on the silicon, the power-delivery network to these buffers, the package interconnects and finally the channel-routing interconnects on the motherboard.
This topology is the design of Intel's current front-side system bus. The bus operates at 800 million transfers, which means the data signals effectively switch at 400 MHz. At such high switching frequencies the room for design error is small, and with the volume of systems shipped, the cost of overdesign can make or break profits. These two factors place a premium on design/simulation accuracy and force the design methods to span all of the subsystems simultaneously to remove the historical fat in bus designs.
The historical design method aimed to individually predict how much of the timing window each subsystem could consume in its worst-case configuration. For example, a 100-MHz front-side bus has an ideal timing window of 2.5 nanoseconds. The I/O buffers were simulated for their output and input timings and jitters using comprehensive circuit simulators. These simulations would cover the entire specification range for the component in terms of voltages and temperatures. The power-delivery network would be modeled to produce a 10 percent variation on Vref, while the simultaneous-switching output effect on the buffers would also be simulated using tools like Speed2000 from Sigrity Inc. (Santa Clara, Calif.). The package would be simulated to check crosstalk and intersymbol-interference (ISI) degradation.
Finally, the motherboard interconnect would be simulated to find a solution space with all of the subsystem contributions included. This final step would linearly add together all the timing numbers from each subsystem and define a set of motherboard design rules (routing lengths and trace spacing) that would provide positive timing margin.
The voltage is common among all these subsystems. Historical methods would often take a worst case from I/O subsystem at one voltage level and mix with the worst case from the interconnect at a dissimilar voltage. The result is that even though the performances of all interconnects were obtained, little was known about the possible design trade-offs that would be available with a co-design of the entire bus. The resulting co-design approach results in a positive timing margin.
This, however, has all changed. The need for speed has pushed design methods into a holistic system-level approach.
The current Intel front-side bus, operating at 800 million transfers with an ideal timing window of 625 ps, does not permit a subsystem approach. Improved design and optimization of the I/O buffers can reduce those respective subsystem timing numbers by up to a factor of two. However, this alone leaves precious few picoseconds for the package and motherboard signal integrity.
Intel's solution is to co-simulate some of these subsystems to reclaim the excess margin associated with the piecemeal approach. Ideally, one would want to co-design the entire system; however, that is not currently feasible. At Intel, we attempt to break the problem into only two subsystems: I/O and interconnects. This is not a 100 percent separation, as the interconnect simulations still use the actual I/O buffers, but it allows for independent I/O simulation and optimization and permits third-party silicon solutions.
The accumulation of the entire bus into one simulation has created a complex and demanding simulation problem. The EDA tools and the computing infrastructure have relieved some of the pressure. However, the very nature of this co-design approach has greatly increased the number of parameters that need to be comprehended. This makes it extremely difficult to model the whole system. A design-of-experiments (DOE) analysis minimizes the number of simulations required while still maintaining a robust set of parameters and provides key information about the interactions between the subsystems.
The central idea behind the DOE and response surface-modeling method is that key design metrics (timing and voltage margin) can be represented as a mathematical function (generally a polynomial) of the input parameters.
An optimal set of "experiments" or simulations is performed to find the coefficients of these functions. It is through these functions that the interactions between subsystems are assimilated and can be explored for design optimization. This optimal set of experiments is the DOE portion of the design method, and the first step in the overall methodology. The optimal set of experiments is determined by the number of parameters and the complexity of the output metric polynomial. The number of experiments does not explode as the number of parameters rises; a 20-variable full-quadratic design would need on the order of 500 simulations.
The second phase is to create the output metric models, which is done using a linear least-squares technique. It is through these "system"-level models that all the benefits of co-simulation can be realized. There are two ways through which the historical fat in our design is reduced.
First, the variables that cross multiple domains are inherently tracked. For example, we eliminate the possibility of the worst-case I/O timing coming from a voltage that does not create the worst-case interconnect ISI. This is achieved simply by the fact that our timing and voltage margin models (functions) are a function of only the global voltage variable.
Second, we realize gains in the interactions between variables represented by the cross-terms in the polynomial expansion. The timing and voltage models contain terms that are combinations of variables for various domains, such as package impedance and motherboard impedance; this results in a more accurate accounting of the entire system.
There are a number of other quite important side benefits of the modeling method. The models provide valuable information about improving designs, such as which variables are the most important and at what ranges. The models allow for quick engineering decisions to get a solution space. The models also provide a valuable tool for correlation to validation and lab measurements. And finally, the models can provide clues as to cost-reducing designs.
In summary, the design of high-speed buses is only possible through the use of the proper EDA tools and effective methods, such as DOE, to co-design the entire bus. The employed DOE approach has been shown to work hand-in-hand with these complex whole-system simulations to provide a tractable design methodology using tools like Speed2000.
Adam Norman, Weimin Shi and Maynard Falconer are staff analog engineers working in the Desktop Platform Group at Intel Corp. (Hillsboro, Ore.).
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