Recent major innovations in packaging technology have led to a number of more powerful and more flexible packages that attempt to cope with the challenges posed by designs containing multimillion gates and multigigahertz systems-on-chip.
While offering numerous opportunities, ball grid array substrates, flip-chip and multistacked dice-often mixing wire bonding and flip-chip contacts-require an unprecedented level of integration between IC and package design and verification. This integration, in turn, requires a change in methodology as dramatic as the one that occurred when logic synthesis and place and route software merged into physical synthesis. Engineers need a new class of EDA tools as well as some training so that IC and package designers can acquire some of the others' skills.
The package is not just a simple one anymore: IC and package have become a whole and must be treated as such. Both technology and economy dictate that much.
Most existing design methodologies, tools and flows result in a segregated relationship between IC and package. The serial nature of the traditional one-way-package-to-IC or vice versa design flows, limits the effectiveness of existing tools for concurrent planning. Both IC and package design tools lack the visibility needed into their respective neighboring environments to be useful. And IC and package designers, who know little or nothing about each other's requirements and constraints, don't make matters any easier. These failings may lead to a poor IC-to-package relationship, resulting in overly complex custom package designs, increased packaging costs, longer cycle times and less-than-optimal IC performance.
Available top-down (package-driven) and bottom-up (IC-driven) flows, which assume that the package is fixed and the IC has to be adapted or vice versa, are no longer adequate. A co-design and co-verification methodology is necessary, which demands a highly automated yet integrated solution.
Ideally, designers should have a unified environment, with a common set of features allowing package and IC to be designed concurrently, taking into account all the constraints at once. An engineer should be able to adopt either flow-top-down or bottom-up-depending on the actual task.
Top-down, package-related information is key to providing IC design-planning tools with reasonable speeds, such as I/O placement, thereby avoiding unnecessary iterations. The IC design tools must be able to import information regarding substrate routing tracks of critical signals, for signal integrity and noise avoidance.
Bottom-up, package physical-design tools must be able to import, from the IC world, specifications and critical information regarding sensitive components, such as memories or analog blocks, in order to prevent the placement of the bumps over them. Redistribution layers information must be available in both worlds.
Increasing I/O density and more and more complex power and ground schemes lead to human errors, which are hardly detectable by visual inspection. It is therefore necessary to apply techniques such as layout vs. schematics at the package-plus-IC level.
On the one hand, by using tools that enable the co-design (and co-implementation) of the IC and the package, engineers can better adapt the IC and package to each other, with obvious implications for cost, performance and time-to-market. On the other hand, having available all the necessary information at both the IC and package level, engineers can co-verify both designs while considering their reciprocal influence, which in turn means higher reliability of the whole system.
Last, a package reuse discipline is becoming a must: Today, each new IC design start often leads to a new substrate design start. The upshot is hundreds of design starts with little chance of reuse and high potential for very expensive substrate scraps should the IC design not go through.
Of course, this is mostly an integration and interoperability issue-typical dull engineering problem-as opposed to the sexy, algorithmic, nonpolynomial-complete problems. Still, it can, and actually does, make our life miserable.
Having worked in the semiconductor industry for the last 20 years, I am still amazed by how the relationship between IC and package has been largely ignored by academics and, until very recently, by the design automation industry.
Have you noticed how the issue of IC packaging, co-design and co-verification has been completely ignored by major conferences? Having attended the Design Automation Conference for several years, I cannot recall any keynotes or special sessions, panels, tutorials or even just papers on this matter.
Too bad for the poor design team struggling with the design of a multigigahertz IC with 20 million-plus gates, to be packaged into a flip-chip ball grid array package with more than 2,000 balls. First, the team must solve the awful hierarchical planning; physical synthesis and optimization; routing; 3-D parasitic extraction; timing and integrity analysis; and formal verification problems. However, after that has been done, it may discover, just too late, that this huge IC does not fit in the target package because of mutually induced substrate noise, or power, or thermal-related issues or that the package is just not economical.
Today, leading OEM customers consider advanced IC packaging know-how to be among a handful of key selection criteria for making their final decisions about which semiconductor company will do their next-generation, 90-nanometer, multimillion-gate and multigigahertz design. Are they not finding this expertise?
I am calling for a necessary, collaborative effort among semiconductor companies, the EDA industry and academia to make available soon such key ingredients as concurrent package, IC physical design, and full package and IC parasitic extraction and electrical characterization.
I have been waiting for 15 years. I think that I-and the rest of the design engineering community-have been waiting long enough.
Marco Casale-Rossi (email@example.com) is EDA partnerships manager at STMicroelectronics (Carrollton, Texas).