YORKTOWN HEIGHTS, N.Y. Researchers at IBM's Thomas J. Watson Research Center here last week detailed a new way of building nanocrystal flash memories that precisely controls the size and position of the nanocrystals.
The methodology is close kin to the normal lithographic process used in fabricating ICs with a set of masks-only instead of photoresists, a polymer template is employed to self-assemble the nanocrystals in the program oxide of a floating-gate flash.
Researchers Chuck Black and Kathryn Guarini will explain their self-assembly method and its similarity to conventional lithography at the International Electron Devices Meeting (IEDM), which opens Monday (Dec. 8) in Washington.
If brought to commercial fruition, the technique could enjoy manufacturing costs and complexity on a par with today's flash production, according to the two researchers.
"In effect, we have combined self-assembly with semiconductor fabrication," said Black. Other attempts at forming nanocrystal floating-gate memories use chemical vapor deposition (CVD) or aerosol deposition.
Guarini described the method as "potentially a cost-effective fabrication technique that at the same time increases the reliability and longevity of flash memories." She added that IBM is "not saying that we will produce flash memories using nanocrystals in the near future." The flash device in fact is a testing vehicle for the IBM Research methodology.
Other uses for the self-assembly polymer approach might be creating three-dimensional ICs, for instance, the researchers said at a briefing in Yorktown Heights. But they cautioned that they are not chasing self-assembling circuits. "That's not a feasible approach today," Guarini said. Rather, "we have developed a polymer template technique that can be applied for more than nanocrystals in flash memories-it can be applied to create denser controllable sections of other chips where this makes sense."
IBM will have plenty of company at IEDM. Also scheduled to discuss nanocrystal flash are engineers from Motorola, STMicroelectronics and Samsung.
The keen interest comes as the nonvolatile-memory community searches for new approaches to overcome the scaling issues for floating-gate flash, said Radu Andrei, an analyst at Web-Feet Research Inc. (Monterey, Calif.). Andrei said STMicroelectronics has indicated it is making good progress with nanocrystal flash. Its IEDM paper will zero in on keeping the threshold voltage uniform across a nanocrystal array, a major challenge.
Also at IEDM, a team from Samsung Electronics Co. (Seoul, South Korea) will present a nanocrystal flash that incorporates a nitride-oxide-nitride stacked-tunnel barrier structure. The NON tunnel barrier enables a 100x improvement in the program and erase speeds compared with conventional NAND-type flash, according to an abstract of the paper.
In their IEDM presentation, Black and Guarini of IBM will describe the potential advantages of nanocrystal floating-gate memories over conventional floating-gate flash devices, including improved scalability, retention and cyclability, as well as lower-voltage operation. In these devices the floating gate is composed of discrete, electrically isolated particles rather than a continuous film.
Nanocrystals formed by CVD or aerosol deposition have a wide distribution of size and position, which leads to limitations on device performance, scalability and manufacturability, said the IBM researchers. In contrast, IBM's method produces silicon nanocrystals that are defined via a polymer self-assembly process, which sets the nanocrystals' dimensions, density and uniformity.
The pair claimed the characteristic dimensions of self-assembled films depend on the intrinsic molecular-length scales. That makes them inherently more controllable than structures defined using deposition processes, whose size distributions are limited by nucleation and diffusion effects, they said. The self-assembly technique results in tight control over nanocrystal size and distribution, allowing flexibility in target particle dimensions and enabling formation of nanocrystals of different materials, Guarini and Black said.
The silicon nanocrystals are defined using diblock copolymer thin-film self-assembly, a process involving spin-coating a dilute polymer solution and annealing to promote phase separation into nanometer-scale polymer domains. The diblock copolymer is composed of polystyrene (PS) and poly(methyl methacrylate), or PMMA, whose molecular-weight ratio produces hexagonally close-packed PMMA cylinders in a PS matrix. The PMMA is removed with an organic solvent, leaving a porous PS film that is used as a sacrificial layer to define nanocrystals at sublithographic dimensions.
The key steps include forming the porous PS film on a thermal-oxide hard mask, etching the PS pattern into the oxide, growing a 2- to 3-nm program oxide and conformally depositing amorphous silicon and then etching it using an anisotropic reactive-ion etching process.
The silicon nanocrystals reproduce the dimensions of the original self-assembled polymer film: They are 20 nm in diameter with a center-to-center spacing of 40 nm in a closely packed hexagonal pattern. The nanocrystal density is 6.510/cm2. The devices are completed by depositing a control oxide of 7 to 12 nm on top of the nanocrystal array, then depositing, doping and patterning the polysilicon gate. A single metal layer is used to contact the gate.
"We have achieved nanocrystal formation that exhibits a precise definition of the tunnel barrier, a well-controlled size and a constant nanocrystal density," Black said. The researchers emphasized that smaller nanocrystal dimensions can be achieved by using a polymer with a lower molecular weight, which could lead to future device scaling.
Devices are programmed by injecting charge into the nanocrystals via the program oxide, and erased by expelling charge from the nanocrystals. "The advantage of nanocrystals is that if one of these loses the charge, you don't lose the entire device," said Guarini. That's because "there are so many more nanocrystals keeping the charge, thus allowing the flash cell to keep working."
The researchers observed acceptable hysteresis curves for storing capacitance over write voltages from -1 V to -6 V over a gate-voltage range of 0 to -3 V.
Additional reporting by David Lammers