SAN FRANCISCO In a technical session at the International Solid State Circuits Conference here Tuesday (Feb. 17) Intel Corp. will quietly signal what may be the company's most aggressive move to influence system memory architectures since the days when it made DRAMs.
In a paper titled, "A 2 Gb/s Point-to-Point Heterogeneous Voltage-Capable DRAM Interface..." Intel engineers will disclose some details of a set of test chips that have validated an Intel-designed high-speed DRAM interconnect scheme. Hidden between the lines, the paper will also disclose that Intel has taken the scheme to two major DRAM vendors who have fabricated test chips of their own.
The effort thus takes on the aspect of an end-run around the ponderous DDR (double data rate) DRAM standardization process, and appears a mortal threat to further major participation in the main-memory interconnect market by Intel's once-beloved partner, Rambus Inc.
The interconnect scheme rests on a number of technical advances in transmitter and receiver circuitry. Primary among them are the ability to conduct simultaneous bi-directional transactions over a single wire, using receivers that perform a simple subtraction to separate incoming from outgoing signals.
In addition, as the paper's title states, the interconnect scheme is point-to-point. Interconnect lines daisy chain from one DRAM chip to another, with carefully controlled clock synchronization to prevent skew from accumulating.
This stands in stark contrast to current approaches, which use a multidrop bus shared by all the DRAMs in an interconnect segment. The multidrop architecture is used by both DDR and Rambus technologies.
By using 1.4V point-to-point links, edge-rate control, selectable reference voltages and careful termination, Intel measures data rates as high as 3.6 Gbits/s per pin, and argues that the scheme is expandable to relatively wide banks of pins. Thus it could form the backbone of large very fast DRAM main memory structures.
In fact, according to Intel director of circuit research Shekhar Borkar, the scheme is scalable enough to cover both quite small and very large arrays of DRAMs, and is readily adaptable to existing DIMM modules and DRAM packages.
Perhaps more important, Intel has teamed with two DRAM vendors, Infineon and Samsung, to demonstrate that the interface circuits can be built in existing DRAM processes with no special provisions, and can operate in existing DDR2 packages.
A paper later in the conference by Samsung will describe in detail their test chip, in which an implementation of the Intel interface replaces the existing I/O strip on a 0.11-micron DRAM die with dummy memory arrays. Intel fabricated its own test chip to simulate the behavior of a DRAM controller, and the companies demonstrated 2 Gbit/s operation over an actual circuit board, and showed convincing eye diagrams for simultaneous bidirectional operation.
By involving two heavyweights of the DRAM industry in the experiments, Intel is signaling its willingness to circumvent the standardization process that is ponderously working toward a faster DRAM interface spec, and to cut a deal directly with the memory manufacturers. It is also signaling, if there were any doubt on the subject, that it sees little role for Rambus and its stripline multidrop architecture in the future of DRAM memory systems.