Tokyo - The argument over whether Sony wrongly claimed that the processor for its PSX game console is a 90-nanometer device devolved into claim and counterclaim last week, as two Canadian engineering outfits took opposing positions over Sony's insistence that the EE+GS@90nm device is fabbed on the bleeding-edge process (see Feb. 2, page 1).
Chipworks Inc. (Ottawa), an engineering services company, entered the debate last week by defending Toshiba and Sony. The company said it considers that the processor within Sony's PlayStation X has been fabricated in one of the most advanced processes in production.
The CMOS4 process that is used to fabricate the EE+GS processor is common to Toshiba and Sony.
Chipworks rebutted claims by another Canadian engineering services company, Semiconductor Insights, which said the EE+GS@90nm chip used in the PSX was manufactured on a "130-nm" manufacturing process, according to measurements it took from multiple sites, which were benchmarked against the International Technology Road-map for Semiconductors (ITRS).
Sony defended its claim, and said it has asked Semiconductor Insights about its measurement methodology.
"Our process is normally regarded as a 90-nm process in the semiconductor industry," Kenshi Manabe, CTO of Sony Semiconductor Solutions Network Co., told EE Times. "The same criterion is applicable to the 90-nm processes of other semiconductor manufacturers, such as TSMC, IBM and Intel," he said. "Gate length is subject to variation. The first metal pitch [of the EE+GS@90nm chip] is 110 to 120 nm, which falls in the 90-nm node."
A photograph on Chipworks' Web site (shown here) identifies a cross section of deep-submicron transistors within the CXD9797GB, the official part number of the EE+GS processor. Two transistors are marked as having physical gate lengths of 45.7 nm and 47.5 nm.
Although Chipworks acknowledged those gate lengths did not meet the ITRS 2003 definition for a 90-nm process, the engineering firm continued to defend Sony, observing that the 90-nm manufacturing process from Intel Corp. is reported to have a gate length of 45 nm, barely different from the smallest gate lengths found in the Sony PSX processor.
Asked last week whether Semiconductor Insights could have missed some more aggressively scaled transistors in its original measurements, Edward Keyes, the company's chief technology officer, said that Sony has never claimed to have such small-geometry, 47-nm-transistor gate lengths in its 90-nm process.
Sony's published claims for the CMOS4 process match Semiconductor Insights' findings of a gate length of 70 nm, Keyes said. Semi Insights has confirmed those measurements and pointed out that that is not consistent with a 90-nm process by the ITRS tables, Keyes added.
Keyes acknowledged it is not possible to measure every transistor but also said it is not necessary, as transistors don't come in an infinite number of sizes.
"Engineers don't have the freedom to alter the gate length," said Keyes.