Figuring out how to integrate more and more analog and digital blocks on a single chip has become a difficult task. A primary challenge is that these mixed-signal blocks have diverse design styles. Moreover, complex interactions among these blocks substantially determine the performance of the system of which they are part. Integration thus requires a dual system-circuit view. Design teams have already started to combine a system-level view of mixed-signal system-on-chip (SoC) design with full accounting for the circuit and physical interactions among these blocks and with their connected environment.
Mixed-signal SoC designs are effectively system designs. Although they may not include a software component, complex signal-processing algorithms are often encoded in these designs. More important, when taken together and combined with their adjacent packaging and connected environment, mixed-signal blocks form a system. This system must meet top-level performance and power specifications-a fact that has implications for the design process.
First, the design process must allow fast architectural optimization with explicit consideration of all architectural parameters. Otherwise, the critically important architecture space could not be covered systematically, with disastrous consequences for design time and quality. Mixed-signal designers know that they cannot fix an inefficient architecture at the circuit or layout level. A performance roof is achieved quickly and no circuit tuner can compensate for it. Addressing this issue requires a clear definition of the architectural design space, including key parameters or variables. Parameterization on a block-by-block basis is most effective, especially if a "canonical" design can be defined. Explicit definition of system objectives and constraints can then be defined and powerful optimization capabilities applied.
Second, the design process must have explicit power/performance trade-off capability. Performance in a broad sense (typically, bandwidth) has always been a fundamental part of mixed-signal design. Power and energy, however, are becoming critical in practically any useful application, wired or wireless. Thus, direct and explicit power/performance trade-offs are a necessity; both numbers need to be provided simultaneously when exploring a particular solution. And the option of considering either of them as an objective or as a constraint must be available.
While fast architectural optimization is crucial, low-level electrical and physical interactions in and between mixed-signal components can be so intense that they must be taken into account when verifying against top-level specifications. Low signal integrity in individual circuits can be an insurmountable burden on overall performance. Such a situation has significant implications on the design process.
First, individual blocks need to be macromodeled from the beginning of the design. System-level parameters, such as various kinds of jitter, must be captured into well-defined parametric models. Power macromodeling is just as important-no system trade-offs can be performed otherwise. Second, circuit and physical interactions between mixed-signal blocks must be faithfully captured. Detailed frequency- or time-domain models are often the only way to account for subtle impedance effects between blocks. Perhaps more important is detailed modeling of the system environment, including I/O-to-package layout, package and off-chip connections. Linear and nonlinear system modeling help with this issue. Since these models can capture manufacturing variability effects, these can be readily brought back up in the chain.
New design processes are responding to the challenge of parallel refinement of system and circuit designs with incremental methodology improvements that link system-level parameter-based views with circuit-based macromodeling, thereby accounting for multilevel interactions. However, key to optimizing the system/ circuit balance is the use of standards for circuit IP "packaging." Fortunately, this work has begun and continues to grow.
Juan-Antonio Carballo (email@example.com) and Raminderpal Singh (firstname.lastname@example.org) are co-chairpersons of the Implementation Development Working Group at the VSI Alliance (Wakefield, Mass.).
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