With gate counts and system complexity growing exponentially, new submicron technologies pose many challenges in both the design and verification domains. Nowadays, many high-performance system-on-chip designs integrate digital cores with mixed-signal intellectual properties (IPs) in order to meet aggressive specifications. Since various disciplines are involved, the full-chip verification of an analog-digital configuration is not a trivial task. To date, most full-chip verifications have focused on the gate-level environment due to the complexity of the transistor-level setup. However, the most reliable path to accurate and rapid system verification should be based on innovations in both tools and mixed-signal methodologies.
Designers need to develop a quality assurance (QA) acceptance flow that minimizes the growing gap between the foundry and IP provider, and allows the detection of a wide range of bugs. An example is Synopsys NanoSim, an advanced transistor-level circuit simulation and analysis tool for analog, digital and mixed-signal design verification.
Traditional verification flow
The VLSI community has practiced the traditional flow for mixed-signal designs for many years. Two separate teams, each with its own expertise, conduct the design phase: One team implements the resistor-transistor logic (RTL) code and the other team designs the analog circuits. In the verification phase, much effort is invested both in the gate-level verification and in the transistor-level verification. Verilog is the most common and most popular language for full-chip gate-level verification. The flexibility of high-level Verilog language, together with a self-checking mechanism, enables the extensive coverage of the entire project in a short time.
However, the behavioral models that are required for emulating the functionality of the analog blocks are the main weakness of the Verilog gate-level verification. Any miscorrelation between the behavioral models and the analog circuits may introduce defects that will later be revealed in silicon. To ensure the correct functionality and the required performance, qualitative transistor-level simulation is required. The concept of look-up tables and circuit partitioning provides Nanosim the advantage in full-chip simulations without significantly changing the accuracy level.
The added value of transistor-level simulation lies in accuracy, interface validation, timing, voltage and power characterization, and, of course, reliability. With regard to accuracy, transistor-level simulation reflects the real silicon behavior, however it depends on Spice models, simulator configuration and the quality of the netlist. Unlike gate-level simulation, which is based on fixed timing files and extrapolation, simulations with Spice models result in higher accuracy.
Interface validation is important because different teams handle the analog and the digital design, making the interface the most sensitive point. In many cases, wrong signal polarity, incorrect voltage levels and timing skew defects can be detected only in the transistor-level verification.
Timing, voltage and power characterization, meanwhile, are particularly important in light of today's low-power/high-speed devices. Indeed, timing and power estimations are fundamental requirements. Simulations in transistor level always highlight hidden faults, which couldn't be seen in a simple gate-level verification. For example, a skew in differential signals, which was not modeled properly in the behavioral model, results in successful gate-level verification but immediately fails in the transistor-level simulation due to major glitches.
For reliable power measurements, only transistor-level simulations can guarantee both the required logic signal state and the accurate transistor power consumption and leakage.
Finally, to ensure long-term operation of the chip, every transistor should operate in its safe area. Special commands for safe operating area checks dynamically warn about any voltage violations in the transistor nodes, ensuring reliability.
Assuming that 70 percent of the overall design phase is dedicated to verification, innovation and more powerful tools are undoubtedly essential. The suggested methodology, as illustrated below, is based on the Synopsys Discovery AMS (Analog Mixed Signal) platform, which enables the simulation of digital core and analog circuits simultaneously.
The main concept is to establish one full-chip verification environment, which then can be transparently simulated in three abstraction levels. Most full-chip design efforts are invested in the first gate-level stage, where extensive test benches are developed.
The second full-chip verification phase is a mixed-mode Nanosim VCS co-simulation with the original analog circuits. This configuration enables the full-chip verification process to begin earlier and to identify bugs before commencing the synthesis phase.
The third phase, the most accurate and time-consuming one, is the full-chip signoff transistor-level verification.
The major advantage of this verification methodology is the reuse of the same Verilog test throughout the abstraction levels. Other benefits include one full-hip verification environment with reused Verilog testbench; simple verification of the analog and digital interface functionality before synthesis; comprehensive functional verification in all the abstraction levels; and integration of both Nanosim and VCS tool features.
With Synopsys' Discovery AMS mixed-signal platform in an IP acceptance flow, the verification capabilities can be greatly enhanced, enabling the detection of a wide range of functional defects and thus producing higher-quality IP.
Shmuel Zagury (email@example.com) is a senior VLSI engineer for Tower Semiconductor Ltd. at the company's Natanya Design Center (Natanya, Israel).
See related chart