The verification of mixed-signal designs shares all the problems associated with verifying digital designs--for example, detecting complex corner case bugs. However, there are two extra problems: the need to verify both a transistor and hardware-description language (HDL) model and the fact that analog simulators are orders of magnitude slower than HDL simulators.
However, it is possible to construct a unified testbench architecture for verifying mixed-signal designs, thereby providing both productivity gains and quality improvements over previous techniques. This methodology has been used to successfully verify several members of a high-speed I/O macro family.
A common approach to the problem of verifying both a transistor and HDL model is the manual insertion of delays into HDL models to match exactly the delay of the transistors at nominal process conditions. The waveforms from simulations of both models can be compared, thus exposing any differences. This technique avoids writing testbenches for each level of modeling. It results in lengthy manual tuning of test cases and delays, however. Decisions must also be made about valid time windows for comparison. By its nature, this tuning takes place at the end of the project, thus incurring unpredictable schedule slips. The usual workaround to the problem of slow analog simulators is to write dedicated tests targeted at particular features with no test quality measurement.
This article describes the creation of a single testbench to verify both HDL and transistor level models, using functional coverage to create an optimal test case suite for transistor-level simulations.
The approach described has been successfully deployed to verify high-speed serial I/O hard macros for integration into ASICs. These are large mixed-signal designs with significant digital and analog content. A transmit macro has a wide parallel input bus and converts this into a serial output for transmission over a printed-circuit board at higher speeds. A receiver macro has a serial input and slower wide parallel on chip output bus. A macro has many different modes of operation controlled by on chip input pins.
The testbench consists of two parts: a stimulus generator and a behavior checker. These are written in a high-level verification language called "e" using a tool called Specman Elite by Verisity. The two sections of the testbench do not communicate directly, only via the simulator. Thus the checker can be used without the stimulus environment in chip-level tests. The usual mode of operation for such a testbench is to run in parallel with an HDL simulator. By communicating directly with the HDL simulation kernel the testbench can stimulate the device under test and observe the responses. Specman Elite does not have a communication interface to any transistor simulator tools. The checker is run as a post-processing step observing the macro behavior via waveform files.
Transistor-level simulations are usually stimulated via a piecewise linear description of inputs. A signal monitor has been written in E to record every change of input stimuli from a HDL simulation and generate a piecewise linear file.
The E language contains constructs allowing access to signals within a HDL simulator. However, this does not support extracting information from a file. Instead, the checker accesses signals via a wrapper module, written twice. The first version uses the E language constructs for signal access; the second extracts data from a file. Both versions of the code have an identical interface to the layer of code above, thus providing an extra layer of abstraction, allowing the checker to be used with any source of simulation data.
In digital design, things are usually black and white. However, in analog design things are rarely that simple--phase-locked loops take time to lock to the correct frequency, bias circuits take time to power up and so on. If the checker begins checking before an analog circuit has reached the operating point a false failure may occur, thus wasting engineer debug time. To deal with this ambiguity the checker contains a data structure called fuzzy. The fuzzy structure contains an element for each mode of operation of the design under test, equal to the maximum response time to the mode changing. On every mode change the checker uses this "fuzzy" information to compute how long to wait before recommencing behavior checking. This automation avoids manual creation of time windows where checking is not valid.
Analog signal checking
In mixed-signal verification it is common to check analog parameters of key signals. These analog properties can be checked by processing the waveform to extract parameters of interest and then reading in to the testbench for checking against expected values.
Verification requires a measurement technique to provide an indication of progress and quality. The most effective approach is functional coverage. Functional coverage collects information on whether interesting scenarios and events have occurred during the simulations providing feedback on what test plan items have not been tested.
Transistor-level simulations of large circuits are very slow. Hence in practice a much-reduced set of coverage must be accepted compared to HDL verification. This reduced suite of tests usually focuses on the interaction between the digital circuits and the analog circuits, as both are thoroughly verified independently of each other. The same functional coverage gathering code used for the HDL simulations can be used to show exactly what functionality has been tested at transistor level. Thus providing an objective measure of the quality of these tests.
Christopher Brown (firstname.lastname@example.org) is a verification engineer at Texas Instruments Inc. (Northhampton, U.K.).
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