The increasing popularity of the 60-GHz unlicensed band for wireless communications, combined with CMOS scaling yielding faster devices, offers a great opportunity for using mainstream CMOS technology for 60-GHz radios. Results presented in February at the International Solid-State Circuits Conference indicate that a 0.13-micron NMOS transistor can achieve a peak of 135 GHz, and by careful design and layout of the active and passive components a standard digital 0.13-micron CMOS technology is capable of 60-GHz operation.
With operating frequency approaching the limits of CMOS technology, modeling accuracy becomes more critical as performance margins shrink. Highly accurate, broadband small-signal CMOS models up to 65 GHz for fixed bias points have been demonstrated recently. This enables the design of linear circuit blocks such as low-noise amplifiers. Voltage-controlled oscillators have already been demonstrated in CMOS operating at 60 GHz, and relatively high-Q inductor-capacitor or transmission-line resonators have been measured in these frequency bands.
Mixers are another critical block, greatly influencing overall design and system performance. Optimizing nonlinear circuits such as mixers requires precise knowledge of the nonlinear characteristics of active devices over a wide range of operation. Challenges in the design and modeling of 60-GHz mixers will be discussed at the Communications Design Conference session "60 GHz and Above: Opportunities and Technologies."
A large-signal CMOS transistor-modeling methodology has been developed that extends the standard low-frequency MOS model with additional parasitics, necessary to account for high-frequency effects. It is implemented by using a core BSIM model for the intrinsic device.
In the millimeter-wave region, it is difficult to obtain high-gain CMOS amplifiers, so the noise requirements for millimeter-wave CMOS mixers are strict. A low conversion loss at low local-oscillator (LO) power is also desirable for a CMOS mixer operating at this frequency range, where it is very difficult to get high LO power out of a CMOS device.
Simpler is best
The design goal of low noise together with millimeter-wave CMOS modeling difficulties limits the use of complex mixer topologies. The Gilbert cell mixer, the workhorse of many low-gigahertz CMOS designs, is complex and requires a differential LO, so simpler architectures may be preferred. Low-loss diodes are not available in a standard digital CMOS process so alternatives such as dual-gate mixer or single-gate mixer topologies are explored.
The core of the dual-gate mixer is a cascode connection of two equal-width NMOS transistors. This configuration is well suited to MOS technology since the drain and source of the two FETs can be shared, thus reducing capacitances at this floating node. The gate of the common source device is driven by an RF signal where its transconductance is modulated by the LO signal applied to the gate of the cascade transistor. This mixer is compact and provides an inherent isolation between RF and LO. Modulating the transconductance by a change in drain-source voltage is only efficient if the transistor is biased at the linear region. Unfortunately, the limited gain of a CMOS transistor operating in that region at 60 GHz reduces this architecture's conversion gain.
In general, active gate-fed mixers display the best conversion gain and noise figure for the least amount of LO power. For a standard CMOS process the transconductance of the transistor can be efficiently modulated by variation of VGS voltage at a gate bias point near the threshold voltage. However, all single-element mixers require hybrid or elaborate power-combining circuitry to combine LO and RF signals. However, because of the high frequency of operation the hybrid can be easily integrated on-chip in a CMOS process. The nonlinear device model and transmission line electrical models were used to design and optimize a mixer topology consisting of two single-gate mixers and a 90 degrees branch-line hybrid. The mixer downconverts from 60 GHz to 2 GHz by using a 58-GHz LO signal.
Sohrab Emami and co-authors Chinh H. Doan, Ali M. Niknejad and Robert W. Brodersen are with the Berkeley Wireless Research Center, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley.
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