Ten years after its market entry as the next generation in synthesis, Synopsys' Behavioral Compiler is dead. Can somebody else breathe new life into behavioral synthesis? If not, SystemC will remain a modeling and simulation language with no automated path to silicon implementation.
The premise of behavioral synthesis is that you start with a high-level description with few implementation details and let the tool handle resource allocation and scheduling. Behavioral synthesis promised much faster design turn-around than conventional RTL coding. But outside of a few specialized niches, designers weren't willing to step up to it.
Aart de Geus, Synopsys CEO, wrote a requiem of sorts for Behavioral Compiler in a recent E-Mail Synopsys User's Group mailing. Synopsys placed both Behavioral Compiler and the related SystemC Compiler on an "end of life" basis earlier this year.
"While behavioral synthesis tools offered some great productivity advantages over RTL synthesis, we found that most customers were either not willing to take the QoR (quality of results) hit necessary to use these products, or they were not willing to complicate their verification flow," De Geus wrote.
Now that all the big EDA vendors have given up on behavioral synthesis, is there any future? Forte Design Automation thinks so. At last year'sDAC, Forte previewed its SystemC-based Cynthesizer tool, and got some good reviews in John Cooley's DAC trip report.
Cynthesizer still hasn't been formally introduced, but you can read all about it at Forte's Web site, www.ForteDS.com.
And now along comes startup Bluespec (www.bluespec.com) with another message: Forget SystemC, and synthesize from assertions in SystemVerilog.
That company is preparing "assertion-based synthesis," in which users define state elements and specify actions in terms of "rules" using SystemVerilog.
This debate could be vital to the future of electronic system-level design. If a SystemC-based ESL market is truly to emerge, and address more than systems architects, behavioral synthesis needs to work. But today's RTL designers may be more comfortable with SystemVerilog assertions. The race is on to see who can produce the best silicon in the shortest time.
Richard Goering is managing editor of Design Automation for EE Times.