Austin, Texas - Taiwan Semiconductor Manufacturing Co. plans to introduce a metal-insulator-metal (MIM) nonvolatile memory at the 90-nanometer node that will have a much smaller cell size than existing memory options, TSMC managers said here recently at the company's technology symposium.
TSMC will begin offering the MIM memory in the latter half of 2005, said Jack Sun, director of logic development at TSMC (Hsinchu, Taiwan).
While the MIM option will require four extra masks, the single-transistor memory will have a cell size of 0.21 square micron, with a cell capacitance of 5 femtofarads. That is about one-fourth the cell size of the company's single-transistor SRAM, called the 1TP, at 130-nm design rules.
At the 90-nm node, the MIM memory will be about one-fourth the cell size of the 90-nm six-transistor SRAM, which has a cell size of 0.99 micron2.
John Wei, platform marketing manager at TSMC, said the single-transistor MIM device will be offered to customers that need more than 8 Mbits of embedded memory. Prototypes will be made starting in the third quarter of 2005, and early production, which TSMC calls "risk production," will begin the following quarter.
110-nm option ready
At the technology symposium, TSMC managers said they are ready to begin production of a 110-nm process, essentially a 10 percent linear shrink of the company's 130-nm process. Wei said many TSMC customers opted to use the 150-nm (0.15-micron) process, saving money on die size compared with the 180-nm process. The popularity of the 150-nm option led TSMC to develop a 110-nm process.
The 150-nm process was a 15 percent linear shrink and required a separate set of design rules, Wei said. The 110-nm process does not require new rules, and customers can "directly shrink their 130-nm designs by 10 percent and get 20 percent more gross die," Wei said. "For large chips, there are some yield advantages. And we estimate an 8 percent improvement in transistor performance in the back end of the line."
TSMC is ready to accept production for what it calls the "LV-plus" version of the process, for low-voltage applications. The 110-nm "G" or general-purpose version will be ready in the second quarter of 2005. TSMC does not plan to offer an LP, or low-power, 110-nm process.
For some customers, the smaller die size could result in a 20 to 25 percent cost savings, Wei said, even though TSMC will charge more for 110-nm processing because the mask costs are "a 40 percent markup from the 130-nm process."
The 110-nm process offers tighter interconnects, he said, and the supply voltage remains the same as for TSMC's 130-nm processes, largely because the gate oxide thickness was not changed.
Even as it offers the 110-nm process, TSMC is telling its customers of the advantages of moving to 90-nm design rules. The 90-nm low-power process will be offered first, before the general or high-performance process offerings, largely because the high-volume cell phone chip customers will be the first to switch to 90 nm.
Wei said the 90-nm process, which will be qualified this summer, will increase the device density sharply: At 130-nm design rules the SRAM cell size was 2.43 micron2, shrinking to 0.99 micron2 at the 90-nm node.
Partly because all of the 90-nm chips will use a low-k process, TSMC expects that most applications will see a 30 percent performance improvement compared with the 130-nm process.