SAN JOSE, Calif. United Microelectronics Corp. executives fired back at a Canadian semiconductor engineering services company's analysis of its 90-nm technology, saying the process can be offered in either a low-k and fluoro-silicate glass (FSG) configuration.
UMC also claims that its 90-nm transistors meet specifications in the International Technology Roadmap for Semiconductors (ITRS) roadmap.
Chipworks Inc. claimed Tuesday (May 25) that the UMC's L90 manufacturing process used in a Spartan-3 FPGA from Xilinx Inc., does not use a low-k inter-layer dielectric, contrary to publicity material.
Chipworks said its analysis of a Spartan chip used FSG not low-k. The copper metal is dual damascene, and no trench etch-stop layers were used, thereby minimizing the effective k-value of the combined dielectric and metal-cap layers.
On UMC's Web site, the Hsinchu-based company made no mention of offering either low-k or FSG for its L90 process. But a spokeswoman insisted that the company's 90-nm process can be ordered in either a low-k or FSG film. "UMC offers customers the option of implementing silicon in either low-K or FSG at 90-nm," the spokeswoman said.
By contrast, UMC's rival, Taiwan Semiconductor Manufacturing Co. Ltd., is offering a 90-nm process, based on a low-k-only configuration.
UMC clarified another matter on Wednesday (May 26). "As far as the claim that our design rules do not meet the ITRS roadmap definition of 90-nm is concerned, it must be noted that although UMC offers a baseline technology for all of its process nodes, we also offer many different process options," the spokeswoman said.
"In particular, we offer several different transistor gate- length options based upon our customer's application requirements," she added. "These range from the 70-nm gate length of our standard process to significantly more aggressive channel lengths optimized for specific customer products. Currently, we are working on products using 90nm with these more aggressive gate lengths."