San Diego - Marking what may be a turning point for chip design, EDA vendors will come to the 41st Design Automation Conference here on June 7-11 with new technology in three areas: electronic-system-level (ESL) design, IC implementation and functional verification. Startups and small vendors are behind many of the announcements.
While many observers see ESL as the next wave of EDA, it's been missing a component: automated synthesis. Several vendors are promising to fill that gap with high-level synthesis, including products that work with SystemC, untimed C++ and SystemVerilog assertions.
In RTL-to-GDSII IC implementation, startups are offering new technology in physical synthesis and routing. In verification, more pieces of the "intelligent testbench" are emerging, and formal techniques are finding broader applications.
Gary Smith, chief EDA analyst at Gartner Dataquest Inc., sees two new trends: the emergence of "algorithmic engine" vendors, which offer ways to offload the main microprocessor by putting algorithms into silicon, and the rise of startups that are challenging "weaker" tools in the IC implementation tool sets of Cadence Design Systems Inc., Synopsys Inc. and Magma Design Automation Inc. "Looks like the concept of the IC implementation tool set isn't a slam dunk after all," he said.
In ESL synthesis, Mentor Graphics Corp. this week will announce Catapult C, which creates register-transfer-level descriptions from untimed C++ code. Mentor claims to have more than 10 tapeouts and to have produced chips up to 50 percent smaller than with hand-coded RTL.
Celoxica Ltd. this week will announce the Agility C compiler, which synthesizes SystemC into FPGA logic. While focused on reconfigurable logic, the tool can also produce RTL code for ASICs.
Taking a different approach, startup Bluespec Inc. is releasing its Bluespec compiler, which produces synthesizable RTL code from input based on SystemVerilog assertions.
Forte Design Systems recently announced production of its Cynthesizer SystemC synthesis tool, which was previewed at last year's DAC. The tool is said to halve the design cycle while producing better results than hand-coded RTL.
Algorithmic-engine startup CriticalBlue will come to DAC with the commercial release of Cascade. The tool takes applications software and synthesizes a hardware coprocessor that accelerates software tasks chosen by the user.
In ESL verification, Cadence and Co-Ware Inc. this week will announce an integrated verification flow involving Co-Ware's ConvergenSC design tools and Cadence's Incisive verification platform. Users explore design alternatives with SystemC transaction-level models. The SystemC model then becomes a "functional virtual prototype" that can be brought into Incisive as a heterogenous simulation model, without recompilation.
Co-verification tool provider Adveda BV will show Univers Modeler, which generates SystemC or PLI wrappers around native RTL simulation models. The tool is said to provide a 100x speedup over RTL.
Summit Design Inc. is adding "native" SystemC support to its Visual Elite modeling and verification product. With Visual Elite 4.0, users can have both a "hardware centric" view of the design structure and a C/C++ view of the language.
Vast Systems Technology Corp. has upgraded its Comet coverification environment with a "virtual prototype constructor" and a "peripheral builder," as well as SystemC support. And Tenison EDA has added an IP export feature to VTOC, which generates C++ or SystemC models from RTL code.
The IC implementation market, according to Dataquest, includes tool suites that provide an RTL-to-GDSII solution. Thus far Cadence, Synopsys and Magma have controlled virtually all of the market, but that may be about to change.
Startup Sierra Design Automation Inc. will come to DAC with Pinnacle, a physical synthesis and prototyping tool that claims a five- to tenfold speedup in design closure time compared with existing physical synthesis solutions. Pinnacle is said to handle a 10 million-gate flat design in an overnight run, well beyond the capacity of existing physical synthesis tools.
Startup Silicon Design Systems Inc. last week announced K-Route, which offers concurrent routing, timing, extraction and signal integrity. By solving those problems simultaneously, K-Route claims to avoid iterations and to replace four or five tools that may have incompatible databases or timing engines. K-Route can also do a final placement on a roughly placed netlist.
As Sierra announced Pinnacle in mid-May, Synopsys rolled out an upgrade to its Galaxy IC implementation platform, including a claimed 100 percent capacity jump for Physical Compiler physical synthesis. The Galaxy 2004 release also claims capacity and run-time gains for the Design Compiler RTL synthesizer, Jupiter design planner and Astro placement and routing suite.
Cadence, meanwhile, hinted when Sierra announced Pinnacle that a new physical synthesis capability was on the way. In the meantime, Cadence has announced a "superthreading" capability that lets its NanoRoute IC router run over a distributed computing network.
Magma is rolling out products for structured-ASIC and FPGA design in time for DAC. Magma also added a Blast Power option to its Blast Fusion RTL-to-GDSII flow, letting designers examine power-vs.-timing and power-vs.-area trade-offs without leaving the Magma environment.
Many third-party vendors are offering products that plug into the IC implementation flow. Ammocore Technology Inc. has upgraded Fabrix, its physical design implementation system, with improved timing and power. Pulsic Ltd. has added floor planning to its Lyric IC router. And Sequence Design Inc.'s new Columbus-NTX provides parasitic extraction for both power rails and signal nets.
Shortening the cycle
Given the oft-quoted statistic that verification consumes up to 70 percent of a chip's design cycle, it's no surprise that this year's DAC showcases some advances in verification. Startup Lighthouse Design Automation Inc. is taking aim at what Dataquest's Smith calls the intelligent testbench, or an automated approach to verification planning and implementation.
Lighthouse's inFact, described as the first intelligent automatic testbench sequence generator, compiles a C++ specification that describes a design's behavior. Executable sequence generators are synthesized that adaptively construct sequences of transactions during simulation.
In formal verification, Jasper Design Automation Inc. is offering JasperGold 3.0. Said to allow a "provably correct design" methodology, it lets designers incrementally verify RTL blocks as the blocks are designed.
0-In Design Automation Inc. is offering Archer CDC-FX, which can automatically synthesize a metastability effect generator into an RTL description. The product thus can verify clock-domain crossing metastability effects automatically, replacing what today is a manual process.
TransEDA says its new VN-Spec coverage tool lets designers start coverage-driven verification earlier, at the specification level. The company is also adding a "coverability analysis" option to its VN-Cover product.
Verisity Ltd.'s SpecXtreme lets designers implement testbench functions on Axis Xtreme emulation hardware. Tharas Systems Inc.'s new version of its Hammer accelerator is said to compile 20 million to 50 million RTL-equivalent gates per hour.
Designers seeking low-cost alternatives to emulation and acceleration systems could look at new FPGA-based prototyping boards, such as ProDesign's ChipIt Platinum Plus and Gidel's ProcStar II.