Colorado Springs, Colo. A pair of revolutionary terabit-router architectures have emerged in recent days to launch divergent attacks on the unified-chassis architectures that dominate at the core of global optical networks.
On one flank, Cisco Systems Inc. has moved to a distributed, clustered architecture that scales to 92 Tbits/second. On the other, Axiowave Networks Inc. (Marlborough, Mass.) is pitching a core router that borrows design techniques from asynchronous transfer mode and time-division multiplexed networks. The moves challenge the unified approaches of core leaders Juniper Networks Inc. and Avici Systems Inc. as well as newcomers Caspian Networks and Procket Inc.
"Everything in the core has been about increasing bandwidth and retaining the best-effort nature of IP [Internet Protocol]," said Mukesh Chatter, founder of both Nexabit Networks and Axiowave. "But we believe that guaranteed priorities and strict service-level agreements will be of greater interest to carriers."
Although Axiowave will not reveal full chip-level details of its XCR128 router while patents still are pending, it is obvious that the design team borrowed queuing and switching approaches from the ATM virtual-circuit model. Chatter said carriers always have favored ATM and frame relay because their switch-based oversubscription models pose a profitable way of filling pipes. Multiprotocol label switching the preferred method of handling IP flows can improve the ability to handle divergent IP traffic types, Chatter said. MPLS, however, cannot approach ATM's jitter and latency guarantees.
"We are basing our system on IP/MPLS, but we are combining that with strict guarantees of traffic performance," Chatter asserted.
Chatter had garnered carrier attention with his first terabit-router company, Nexabit, before Lucent Technologies Inc. bought that company for $900 million
in June 1999. Several members of the design team formed Axiowave soon thereafter, inviting Analog Devices Inc. founder Ray Stata to join as chairman.
The lesson Axiowave took from the recession is that carriers cannot make money by emphasizing best-effort IP traffic; they instead must concentrate on premium voice and low-latency data traffic, preserving all latencies for that traffic even in the presence of oversubscribed best-effort IP data.
"The industry mistake lay in thinking that MPLS alone would take care of the profit for carriers," Chatter said. "MPLS cannot provide enforcement for SLAs [service-level agreements], which is the only path for profitability for many carriers."
The XCR128 will scale to multiple terabits, Chatter said, but its basic port granularity will be 10-Gbit OC-192, reflecting the popularity of that Sonet rate and its 10-Gbit Ethernet equivalent.
PowerNet Global, an Ohio-based alternative carrier, has deployed an XCR128 router in its network, according to Axiowave.
While Cisco developers would not take exception to Axiowave's adherence to IP/MPLS or to its advocacy of strict service-level agreements, the router pioneer has elected to throw bandwidth at the problem in massively unprecedented fashion.
Cisco has dispensed with its high-end 12000 architecture in favor of a multishelf, clustered approach wherein one system can sustain 1.2 Tbits/s of performance and 72 linked shelves can realize 92 Tbits/s. The question now is whether the new Carrier Router System (CRS-1) family's architectural departures and reliance on 40-Gbit/s line-card interfaces might prove too large a leap for some carriers.
Starting from scratch
CEO John Chambers said the company had pondered extending its 12000 core-router family but had "quickly determined we needed to start from scratch." That meant moving to a multishelf architecture, with a massively parallel packet-forwarding ASIC at the heart of each router line card, and shifting to a microkernel-based modular operating system that would allow higher-availability processes than the traditional, unified Internetwork Operating System accommodates.
Some competitors are taking heart in the radical break: By insisting that high-end scalability requires a shift to CRS-1 hardware and IOS XR software, they said, Cisco might have done them a favor.
"The specs look good, but a turn to modular software can be a Pandora's box," said G. Hudson Gilmer, senior product manager at Avici. "Can you prove testability without a unified software model?
"The other risk they run, that we'd look to take advantage of, is the announcement of new systems replacing the old before the new ones are in the pipeline. Car manufacturers understand the problem of not preannouncing before you're fully ready to ship, and our customer base tells us that HFR [the original code name for CRS-1] ain't fully baked yet."
Sprint signs on
Cisco, however, announced that Sprint already has a single-shelf production unit of CRS-1 and that additional systems will ship in July.
Mike Volpi, senior vice president and general manager of Cisco's routing technology group, said traditional core-router architectures cannot move into tens of terabits of performance, nor can they offer in-service upgrading of both hardware and software, a capability claimed for the CRS-1.
Cisco spent close to $500 million on research for the CRS-1, which sports 40-Gbit/s line-card hardware as a basic granularity level. The system features a 40-Gbit forwarding ASIC, called the Silicon Packet Processor, and a 40-Gbit packet-based line interface meeting Sonet carrier levels of OC-768c/STM-256c.
While demonstrations in San Jose, Calif., last week featured what Cisco called "the first true 40-Gbit IP network traffic," some analysts wondered how quickly core networks will upgrade from 10 Gbits/s. Drew Lanza, principal with Morgenthaler Ventures, said 10-Gbit channels will be the "747 airliner for the transport industry, becoming a workhorse that won't be upgraded to 40 Gbits for a long time."
Cisco worked with IBM Microelectronics to develop eight ASICs for the CRS-1. The Silicon Packet Processor implements 188 massively parallel RISC cores in an 18 million-gate CMOS device with 8 Mbits of embedded memory. The switching-fabric ASIC, called Sea, implements a three-stage Benes nonblocking switch network with more than a hundred 2.5-Gbit/s channels. The six other ASICs are distributed among line cards and switching-fabric cards.
While the IOS XR preserves the routing software services of the original real-time OS, it allows the distribution of processes and subsystems to be doled out across thousands of processing resources. XR was developed specifically for the multiprocessing Silicon Packet Processor and the multishelf expandability of the CRS-1's line-card and switch-fabric shelves.
XR implements nonstop packet forwarding, stateful switchover and in-service upgrades. The craft interface is based on XML scripts, and network managers can use Cisco's Route Policy Language to set routing domains using a high-level interface.