HONOLULU Micron Technology Inc. unveiled a DRAM architecture that combines a new capacitor with the 6F cell design the company first introduced in 2003.
Speaking at the 2004 Symposium on VLSI Technology here on Tuesday (June 15), Fred Fishburn, a process integration manager based in Boise, Idaho, said the 6F cell size is 25 percent smaller than the 8F designs used by most DRAM makers. "F" refers to the smallest printable feature size of the lithography used in the process. In this case, Micron is using a 78-nm half pitch to create a cell size of 0.036 microns2.
The architecture will used to mass produce devices that will be introduced to the market at the gigabit density and higher, he said, supporting the DDR2 and DDR3 standards. The smaller cell, when combined with peripheral logic circuitry, results in a die size reduction of 18 to 20 percent, he added.
Micron engineers developed a metal-insulator-metal (MIM) capacitor based on a mixture of hafnium oxide and aluminum oxide, which differs from the hafnium-oxide-based capacitors used by most DRAM manufacturers thus far, he said. Aluminum oxide adds good leakage characteristics, while hafnium oxide has a high dielectric constant.
The two materials are deposited in succession with atomic layer deposition techniques. The company claims a 50- percent leakage reduction compared with a hafnium-oxide capacitor. The capacitor has a 25 femtoFarad capacitance.
"We first introduced a 6F cell design in 2003," said Fishburn. "With this work, we are showing its extension to a 78-nm process." Asked if Micron was close to introducing the process, Fishburn said it was, but added that "we still have a lot of work to do."
One participant at the VLSI symposium, who asked not to be identified, said "this is solid work, because it uses conventional manufacturing techniques, without using any exotic materials. The cell size is impressive, and the capacitor shows good engineering."