LONDON Renesas Technology Corp. has developed an SRAM memory cell it claims can reduce soft error rates while reducing cell size and power consumption compared with previous Renesas products.
Renesas said Thursday (June 17) that its "SuperSRAM" technology would enter commercial production for a 16-Mbit low-power SRAM for mobile applications; a 32-Mbit device will follow within a year, Renesas said.
The memory cell allows the fabrication of compact SRAMs, which Renesas expects will displace psuedo-SRAMs that use a DRAM core for mobile applications. The static nature of SRAMs minimizes power consumption, but SRAMs' built-in process technologies have problems with retaining data due to soft errors.
The superSRAM replaces the two load MOS transistors in a conventional SRAM with two thin-film-transistors located above the other transistors. It also includes two cylindrical, DRAM-style capacitors stacked on top of the node, Renesas said.
The design achieves a memory cell size of 0.98 microns2 in 0.15-micron manufacturing process, Renesas claimed. The use of DRAM cylindrical capacitors at the storage nodes has increased capacitance compared with CMOS-type SRAMs, and provides a structure in which soft errors do not occur.
In addition, a data retention current of less than 1 microamp was achieved, Renesas said. Existing process technologies can be used, which should enable speedy market introduction of the devices.