SAN JOSE, Calif. Cadence Design Systems Inc. is making progress toward addressing new problems popping up in "deep nanometer" IC design and is listening more closely to customer requests.
Ted Vucurevich, CTO of research and advanced development at Cadence, stressed those themes in his wrap-up speech at the International Cadence Users (ICU) conference.
Vucurevich said Cadence, which fell behind in the implementation market five years ago, has now recovered and is in the midst of a renaissance.
"We are fostering an innovation-driven environment because quite frankly I never want to see Cadence where we were over the last five years. I don't want to be behind," he said. "The only way we are going to be lean, mean and fast is to listen to you, understand what you mean and make the appropriate investments early enough so we can bring those technologies to market."
In an earlier keynote, Vucurevich placed special emphasis on how designs are becoming more complex and thus more expensive with each shift in process technology. He noted that in 1981 it took about 100 design engineer months and $1 million to produce a microprocessor. Those figures jumped to 30,000 designer months and a $300 million by 2002.
Citing a study by researcher Collett International, Vucurevich said functional verification, noise, power dissipation, analog effects and design for manufacturing were the main reasons for respins, thus the main causes of increases in engineering months and costs at the 180-nm node.
Vucurevich said a later Collett study found that respondents producing 130-nm designs indicated functional verification and noise were identified less frequently as the top causes of respins.
Vucurevich said this is in part because EDA companies introduced better tools and methods to address functional verification and noise. But as process geometries shrink, functional verification, noise, power problems become amplified and newer problems in design for manufacturing realm pop up.
For example, Vucurevich said process variability, especially at 65 nm, will be harder to characterize and will adversely affect clocking. "We must learn how to make our designs more robust in the face of that variability," said Vucurevich. "We'll start seeing the harbingers of that analysis requirement in the future."
Vucurevich said analog becomes a bigger problem, too, at 65 nm, requiring detailed characterization and modeling. Power and thermal issues are also compounded as process geometries shrink.
He noted that software is becoming a larger part of the design process. "We've focused on integrating into our platforms the notions of methodology, technology, intellectual property focusing on the different target areas to allow you to get through the design process more safely," said Vucurevich.
During the users' group wrap-up, Vucurevich listed users' requests collected during the conference. He said users requested Cadence support for SystemVerilog and a batch physical verification tool to recapture the DRC/LVS market.
Earlier this week, ESNUG and Deepchip.com proprietor John Cooley presented results from a Cadence user survey in which Assura, Cadence's DRC/LVS product, was most frequently cited as the company's "worst product."
Users also requested that Cadence develop a static timing tool to give users an alternate to Synopsys' market dominant PrimeTime static tool. "That's great," he said. "I think we can do it."
Judging from applause during Vucurevich's wrap-up speech, the top two users requests were that Cadence stop renaming its products and that it simplify its tool licensing. Those were also top issues in Cooley's survey.
Users also requested that Cadence address support response times, and make information on SouceLink and product documentation easier to find.