SAN JOSE, Calif. Hardware-assisted verification tool vendor Tharas Systems Inc. has been awarded four patents its said are key innovations in hardware assisted debug and verification.
U.S. Patent numbers 6,629,297, "Tracing the change of state of a signal in a functional verification system," and 6,625,786, "Run-time controller in a functional verification system," enable Tharas to embed debug infrastructure inside the hardware-assisted engine. Using the infrastructure, it said designers can gain visibility over signals during an entire duration of the test without reconstruction, said the company.
U.S. Patent numbers 6,691,287, "Functional verification system suited for verifying the function of non-cycle integrated circuits (IC) design," and 6,629,296, "Functional verification of cycle-based integrated circuit design," enables delivery of cost-effective and scalable solutions for high-performance, hardware-assisted verification in complex, integrated systems. It covers the fundamental chip and system technology along with its applications towards functional verification.
Together, Tharas now has been granted seven patents by the U.S. Patent and Trademark Office.