SAN JOSE, Calif. The Semiconductor Research Corporation (SRC) and the Semiconductor Industry Association (SIA) are co-sponsoring a contest in which they will be awarding a total of $75,000 to North American universities whose students come up with the most novel, low power designs.
According to the contest sponsors, the contest will be conducted in two phases, with prize money going to the winners in each round.
In phase two, contestants will submit chip designs using novel architectures or subsystems that exploit the advantages of greater systems integration. The phase one first place winner's engineering department will be awarded $7,000, second place gets $5,000 and third, $3,000.
In phase two, the top five entries from phase one will complete their layouts and submit their designs for fabrication on a 180- nanometer, mixed-signal CMOS process at MOSIS. Major partner companies providing funding for the fabrication phase of the challenge include: AMD, AMI, Analog Devices, Cadence, Freescale, IBM, Intel, National Semiconductor and Texas Instruments.
The phase two winners' respective engineering departments will be awarded cash prizes of $25,000, $15,000, and $10,000 for first, second, and third places.
Initial 4-page white papers are due no later than 20 January 2005.
For further information visit SRC's website.