SAN JOSE, Calif. The latest release of Lattice Semiconductor Corp.'s ispLEVER features upgrades to the PLD design suite's performance and functionality.
The company said with the 4.2 release, the company has optimized the place and route software so that the runtimes are reduced 24 percent over the previous version of the tool.
Other suite enhancements include an I/O Assistant for efficient placement of mixed I/O types, the addition of new Power Calculator and ispTRACY Logic Analyzer tools, a new Project Creation Wizard, major upgrades in static timing analysis, floorplanning and DSP design, and the use of the latest version of a Lattice only version Mentor' Graphics' ModelSim simulator.
The new I/O Assistant in ispLEVER now allows users to define the FPGA I/O structure and perform I/O design rule checking early in the design process. This said the company allows users to make critical I/O placement decisions prior to place and route activities, which particularly valuable for larger projects where design teams must define their I/O strategies for multiple modules early in the design process.
Version 4.2 also includes a "Project Wizard" feature, which guides new users through the Lattice flow.
The suite also now offers users a greater breath of Lattice-specific HDL design preference options, providing users more alternatives to choose from to help them optimize their logic in Lattice FPGA architectures.
The latest release of ispLEVER includes a Lattice-only version of Mentor Graphics Leonardo Spectrum synthesis product as well as Mentor Graphics ModelSim 6.0 tool, which features speedier performance than the previous Lattice-only version of ModelSim.
The ispLEVER 4.2 tool suite also includes Synplicity's Synplify 7.7 as a standard feature.
The ispLEVER 4.2 tool suite also adds to the breadth of the ispLEVER blockset for Simulink functions targeting the LatticeECP-DSP architecture. These blocks can be used to build DSP solutions in the MATLAB/Simulink design environment, available separately from The MathWorks.
Design support for the LatticeECP/EC FPGAs has also been expanded to include the Lattice ispTRACY Logic Analyzer tool. Using ispTRACY, the designer can probe and analyze signal activity in the internal nodes of a physical FPGA during operation on a board, said the company.
List prices begin at $995. Customers with current maintenance agreements will receive the ispLEVER 4.2 upgrade at no charge.