Signal integrity issues such as crosstalk delay and noise are significant challenges for system-on-chip designs at 130 nanometers and below. At such process nodes, preventative measures to mitigate SI effects must be taken before the final stages of physical design, or unpredictable timing closure iterations, tapeout delays, chip failures or poor manufacturing yield-perhaps all of the above-are likely to result.
Fortunately, several years of experience with SI at very deep-submicron geometries have led to efficient methodologies throughout the design flow for preventing, detecting and fixing SI effects.
This article summarizes many of the do's and don'ts of system-on-chip design to yield "best practices" for applying an SI-aware flow throughout the design cycle to achieve an SI-clean tapeout in the shortest amount of time. The guide focuses on advanced techniques that have proved effective in achieving SI closure on real-world chip designs.
Have a good subflow for finding and fixing specific SI problems after routing. Preventing signal integrity issues proactively at the front end of your design flow is just as important as fixing SI problems at the back end.
Make timing margins big enough to account for the added delays. At 90 nanometers, most paths show some amount of SI-related delay. It is impossible to fix every SI problem in a 90-nm design, so setting margins higher at the beginning of the flow and progressively relaxing those margins works well for any technology.
Adjust placement to minimize the distance between drivers and pins. This is an example of how some methods for preventing SI problems are simply good design practice.
Implement everything possible to reduce routing congestion, which helps reduce crosstalk. Easing congestion across the entire design and in specific local areas also makes SI problems easier to fix later because space is available for moving victim and aggressor traces apart.
Triple-space clock network tracks, shield clock traces, constrain clocks to separate metal layers and/or use higher-layer metal. Clock trees deserve special care because their many levels of logic can accumulate crosstalk-induced delays, and they can be difficult to fix after routing. Be aware that triple spacing may be insufficient, and shielding may lead to additional delay, so use inverters and balanced buffers to minimize rise-vs.-fall skew.
More important, scale up drivers for both clock trees and other nets that are likely to be crosstalk victims so these nets are less susceptible to aggressors. You can encourage stronger drivers by setting aggressive transition times. As you reduce max_transition constraints, area gradually increases until a point at which it increases dramatically. So, set max_transition values just above this knee in the curve.
In some 90-nm designs, that point is below 400 picoseconds, so the range between 1 nanosecond and 500 ps may be good. In general, however, max_transition needs to parallel library characterization values, and most libraries have index points upward of 1 ns.
Leave your SI work until after routing. At process nodes of 150 nm and below, SI-aware design planning is essential to avoid last-minute SI panic.
Use too many long wires, which can cause cross-coupling problems. A specific method is to constrain maximum net length in synthesis and routing.
Push area recovery too far. Area recovery is necessary to conserve space, but don't take it too far on paths that are close to zero slack, because they could become SI victims.
Get carried away with scaling up drivers. Stronger drivers take more area and power, and the driven nets are more likely to become crosstalk aggressors themselves. Instead, set max_transition constraints aggressively at the placement\and optimization stage, and relax them a little at the post-route stage.
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