SAN JOSE, Calif. EDA startup Blue Pearl Software Inc. has announced the release of its first product, Indigo RTL Analysis, for rapid functional closure.
According to Blue Pearl, Indigo accelerates designs through the synthesis flow by identifying functional issues in RTL designs prior to synthesis, reducing the number of design iterations required to resolve issues such as synchronization of data crossing clock domains and logic races.
Indigo uses a proprietary high-level functional analysis technology that performs analysis at the full chip level, without synthesizing to gates, allowing it to rapidly analyze multi-million gate designs, the company said.
The tool according to the company analyzes multiple clock domain designs to ensure that data crossing domain boundaries is synchronized. Indigo recognizes double register, memory and custom synchronization schemes and highlights data that re-converges from independent synchronizers. The tool also identifies race conditions, such as write-write, read-write, and combinational loop races, and automatically pin-points the lines of source code that cause them.
The tool also includes traditional built-in rule checks that enforce existing design methodologies, including design reuse (RMM/SRS), design for testability (DFT), simulation, synthesis, and lint.
The company said it will release a timing closure product later this year.
Indigo runs on Solaris, Linux, and Windows, and supports Verilog. VHDL and SystemVerilog support will be available later in 2005. Pricing starts at $5,000 for a one-year, time based, single user license.