SAN JOSE, Calif. Synplicity Inc. has released a new version of its Synplify Pro FPGA synthesis tool boasting major run time and quality of results improvements largely gained through close integration with third-party formal verification, place & route, and debugging products. The latest version also features support for an early subset of System Verilog.
Synplify Pro 8.0 includes formal verification flow support for Cadence's Conformal and Prover Technology's eCheck equivalence checker, which allows Synplify Pro optimizations to be used with popular formal verification software solutions.
The company said the Synplify Pro 8.0 software writes out a verification interface file (VIF) for use with formal verification flows targeting Altera and Xilinx devices. Formal verification tools, such as Prover Technology's eCheck, can now read the optimizations performed by the Synplify Pro synthesis software and perform logical equivalency checking.
Cadence's Conformal LEC product extends equivalency checking to FPGAs through the Synplicity design flow for Altera and Xilinx devices. As announced by Cadence in November, Conformal checks the functional equivalence of designs at various stages, allowing designers to identify and correct potential errors.
The tool also includes tighter integration with place and route tools from Actel, Altera and Xilinx, making it easier for users to run place and route after synthesis and manage the results in the Synplify Pro project, the company said.
Synplicity has also integrated its Identify FPGA source code debugger into the Synplify Pro.
Version 8.0 also includes support for a subset of the System Verilog specification. For example users can implement simplified named port connections using ".name" and implicit port connections using ".*" and 'always' procedural statements.
The company said the log file generated during synthesis by the Synplify Pro software is now HTML based, allowing specific sections to be more easily navigated and viewed. Users also have the ability to filter out certain errors and warnings, enabling them to focus only on new errors and warnings that occur with the latest synthesis run.
The Synplify Pro has a new command line tcl find feature that allows designers to use expressions and operators to find and collect specific elements in their design and then perform operations such as add, union and difference. With this feature, the company said users can analyze their FPGA design and create very specific design constraints for improved performance. A true dual-write RAM support feature is also provided to enable the Synplify Pro software to select the correct RAM implementation for the users' target FPGA device.
Lastly, version 8.0 also includes new device support for Actel's newly announced ProASIC3 FPGAs as well as Altera's HardCopy II family of structured ASICs.
The Synplify 8.0 software is available now starting at $9,500.