Traditionally, designers have built supply rails with little concern about current/resistance (IR) drop and electromigration. For earlier technologies at 0.18 micron and above, designers could confidently assume that power rail integrity would at worst remain a secondary cause of silicon failure. Any impact of IR drop on performance could be ignored by overdesigning and utilizing conservative, oversize power routing-an approach that also provided confidence that power routing would not suffer from electromigration issues. Down to 130-nanometer technologies, insignificant device leakage meant design teams could use liberal amounts of decoupling capacitance to tame IR-drop transients, an approach that remains effective today. At and beyond 90 nm, device leakage rises, forcing design teams to trade off decoupling capacitance vs. increased power consumption. In moving to advanced process technologies at 130 nm and below, however, designers suddenly find themselves confronting the fact that IR drop can cause additional setup-and-hold timing violations that will result in silicon failure. Further, increased power demanded by the chip causes higher current densities within the power routing, and electromigration once again becomes a concern. To avoid power rail integrity problems, designers need to approach power rail design more methodically.
Use proven power rail analysis solutions to help understand the performance of all your power rails, from initial creation to tapeout. For most of today's designs, power rail interconnect is too complex for back-of-the-envelope calculations to be accurate.
Plan your power distribution carefully and perform up-front experiments to understand some of the basic characteristics of your design components. Learn how library cells are affected by IR drop, evaluate the pitch of power straps, determine the worst-case process corners for analysis and understand the impact of adding local decoupling capacitance.
Use static power rail analysis to understand the general robustness of your power rails and to check for electromigration. Use dynamic analysis to optimize decoupling capacitance and perform power integrity verification for analog circuits.
Look at the impact of IR drop on path delays using a proven, IR-drop and signal-integrity-aware delay/timing calculator. This calculator can accurately model the nonlinear impact of IR drop on delay and signal integrity. Remember that the final goal is to prove that power integrity issues are not causing timing or functional problems.
Perform accurate, signoff power rail integrity analysis on the complete design prior to tapeout. Check each operating mode for potential IR-drop problems. Test modes create significant simultaneous-switching events, which can cause silicon failure due to transient IR drop.
For 130-nm and larger technologies, add as much decoupling capacitance as possible after your design has completed routing. Device leakage is small, and additional decoupling capacitance helps minimize any transient IR drops.
Ignore power integrity. The number of designs suffering from IR drop and power rail electromigration-related failures is increasing with each process node.
Rely on engineering judgment and overdesign. Blindly trusting old assumptions is asking for silicon failure. The interdependence of physical and electrical effects at nanometer line widths can easily lead to new problems that quickly invalidate old, familiar design practices.
Use only a vector-based dynamic solution unless you are certain that you have the "right" power vectors to execute. Identifying the vectors that cause local IR-drop hot spots within random logic is difficult. Using an incomplete set of vectors will leave holes in the power rail analysis.
Assume that adding decoupling capacitance is a panacea for transient IR-drop problems. Decoupling capacitance will not completely address high-transient IR drop, which is partially caused by high dc current flowing through resistive power routes.
Ignore the impact that custom and intellectual-property (IP) blocks can have on overall power integrity. Incorrect or inaccurate modeling of these blocks can mask potential electromigration or IR-drop issues.
Steffen Rochel (email@example.com), design-for-manufacturing engineering group director for Cadence Design Systems Inc. (San Jose, Calif.)
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.