MANHASSET, N.Y. Tapping into a growing Indian IC design market, Cadence Design Systems Inc. has renewed an agreement giving India-based Wipro Technologies access to its EDA software. Cadence also announced that Wipro has taped out its biggest chip to date using Cadence's SoC Encounter tool suite.
Cadence (San Jose, Calif.), has been a supplier for Wipro, a global provider of product-design services for semiconductor, automotive electronics, consumer electronics, telecom, networking and industrial automation markets, for the past ten years. Wipro is using a number of Cadence tools for digital and analog IC design, verification, silicon-package-board, and design for manufacturing.
Wipro claims to have recently taped out a 7 million gate, 130 nm, 433 MHz design using SoC Encounter. Wipro has access to Cadence tools including RTL Compiler, First Encounter, NanoRoute, CeltIC, Incisive verification, Conformal, Virtuoso, VoltageStorm, Allegro, and SpecctraQuest.
Wipro is leveraging Cadence's design capabilities to support development of high-end ASICs, complex FPGA and board designs, and turnkey system designs and core technologies across 180 to 65-nm process nodes.