MUNICH, Germany Intel Corp. may drop the use of a high-k dielectric in the transistor gate stack at the 45-nanometer manufacturing process node, according to Paolo Gargini, Intel Fellow and the company's director of technology strategy.
Gargini, added that the company is working on a second high-k material, with a yet higher dielectric constant, but emphasized that the company's process technologies beyond the 65-nm node are not fixed. He said engineers were being encouraged to find a different engineering solution to the use of high-k.
All the leading chip makers have conducted research looking for replacements for the industry's workhorse gate insulator, silicon dioxide, which it was thought would be unsuitable for transistors at 45-nm manufacturing process node and finer geometries, due to excessive gate leakage currents.
Intel itself announced that it had identified a high-k insulator and metal-gate materials in the plural suitable for use in Intel's 45-nanometer generation P1266 manufacturing process due for introduction in 2007, in November 2003. The company has resolutely declined to reveal its choice since then. Gargini also declined to identify Intel's high-k material and metal gate or other gate structures. "It's a secret," he said.
Other industry players have been more forthcoming, with nickel-silicide gates over hafnium oxynitride mixtures emerging as the material system of choice, albeit one that was beginning to cause flutterings of engineering disquiet at the IEDM conference in December 2004.
According to Gargini, Intel's high-k solution allows the 1.2-nm thick film of silicon dioxide gate insulation, used in Intel's 90-nm and 65-nm process generations, to be replaced with 3.0-nanometers of the new material while achieving less than one hundredth of the gate leakage current. "We've got this in our back pocket. If we see a threat we'll introduce it," Gargini said.
When challenged that the conventional wisdom was that semiconductor makers had to go to high-k dielectrics and metal-gates, Gargini said: "It's an option for 45-nm. We've told the engineers we'll pay them more if they can avoid putting it into production." Gargini added that the use of high-k dielectrics would involve a minor additional complexity to the manufacturing process and thereby add a few percent to production costs, but that Intel was always looking for pragmatic ways to avoid or delay making such changes.
"If we can delay the introduction until 2009 we will. It's not decided yet.
One way that Intel was able to continue with silicon dioxide gate insulation material was by understanding how overlayers, such as silicon nitride, and doping could be used to introduce tensile and compressive strain in a transistor's semiconductor channel.
Using cross-sectional diagrams Gargini showed how Intel had used germanium to dope sources and drains in the 90-nm p-channel transistor to introduce compressive strain and used a silicon nitride overlayer to introduce tensile strain in 90-nm n-channel transistors. For the 65-nm transistor he showed a single slide and said the silicon straining had been "enhanced for performance and power efficiency" leaving it unclear whether Intel had again used germanium to swell up the source and drain regions.
While Intel' apparently has a stable first choice high-k dielectric material with an effective constant three times higher than that of silicon dioxide, the company is already working on developing a second generation material with an effective constant five times higher than that of silicon dioxide, Gargini showed in a slide.