LONDON Foundry chip maker Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) unveiled its 65-nm manufacturing process at its Technology Symposium held in San Jose, California Tuesday (April 26), declaring that first wafers processed with the rules are expected in December.
TSMC said FPGA maker Altera Corp. (San Jose, Calif.) and other customers have taped out 65-nm designs and received functional prototypes of 65-nm designs, including devices with areas of logic and memory, for initial validation and benchmarking. Engineers at multiple companies are designing to the process, and tapeouts of production devices are expected to reach TSMC in the second half of 2005, the foundry said.
The 65-nm logic manufacturing process for system-on-chip (SoC) design would allow designers to build circuits with double the density of the company's 90-nm manufacturing technology, TSMC claimed. The increased integration is driven by the ability to increase functionality at a given die area and cost, or reduce die area and cost for a given function.
It is usual to produce several manufacturing process variations at a given geometry node with each optimized in different ways for low-power consumption, for high performance, or general-purpose applications.
TSMC's first 65nm "Nexsys" technology, due to enter production in December 2005, is optimized for low power. A high-speed version would become available in 2006, followed later in the year by a general-purpose 65-nm process, TSMC said. A version employing silicon-on-insulator technology and an ultra-high-speed version would then be introduced in 2007. Logic and mixed-signal options are slated for all versions, with embedded memory available in each.
Comparing its general-purpose processes TSMC's said the 65-nm Nexsys technology would provide a 50 percent speed gain versus its 90-nm process; and a 20 percent standby power reduction. TSMC is also including an electrical fuse technology in its processes to facilitate identification and configuration of devices.
Early design rules and SPICE models for the new technology have been developed and TSMC libraries would be available in the fourth quarter of 2005, TSMC said. Third party library and IP developers are developing additional offerings.
The 65-nm process includes the use of strained silicon and nickel silicide and is the third generation of TSMC process to employ low-k dielectrics and the fourth generation to use copper interconnects, the company said.
In addition, the 65-nm process may be the first-generation process to use immersion lithography for circuit definition. A leading proponent of immersion techniques, TSMC took delivery of the first production-worthy 193-nm wavelength immersion lithography system in 2004. The 65-nm process is due to manufactured in in TSMC's 300-mm manufacturing facilities, Fab 12 and Fab 14.
"TSMC is already the foundry leader in 0.13-micron-and-below manufacturing technologies, with volumes and revenues that are multiples ahead of our nearest competitors," said Kenneth Kin, senior vice president, worldwide sales and service at TSMC. "The new 65-nm Nexsys technology represents yet another leadership point from which the industry can rapidly accelerate the pace of innovation."