SAN JOSE, Calif. Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) on Tuesday (April 26) presented a sneak preview of its 45-nm process technology, which is due out in the 2008 time frame.
The silicon foundry giant plans to deploy copper-interconnects, ultra low-k dielectrics and immersion lithography at the 45-nm node, said Shang-yi Chiang, senior vice president of R&D at TSMC.
TSMC is exploring high-k dielectrics for gate stacks, of which it would like to use at the 45-nm node, according to analysts. But Chiang does not believe that high-k dielectrics would be ready for the 45-nm node, forcing the firm to extend traditional silicon dioxide materials and other technologies in the arena.
"My personal opinion is that (high-k) will not be ready," Chiang in an interview after a keynote address at the TSMC Technology Symposium. "The materials are very difficult."
In a keynote address, the TSMC technologist said that the foundry giant is researching high-k, based on hafnium materials. But the company believes that it can gain more improvements in transistor mobility by using a proprietary strained-silicon technology.
Chiang did not provide details about the technology, but noted the company plans to move towards a new low-k material at 2.4-to-2.5 for 45-nm, based on carbon-doped oxide technology.
TSMC's 45-nm process will move into "risk production" in 2008, he added.