AUSTIN, Texas Faced with increasingly complex cellular handsets, Intel Corp. is pushing for a common bus specification that would be used by different types of memories within cellphones, said Mark Leinwander,
system architecture manager at Intel's flash products group.
Intel currently chairs a JEDEC (Joint Electron Device Engineering Council) committee that is studying the issue. Now, different types of execution buses are used for DRAMs, flash, and pseudo static (PSRAM) memories. That makes it difficult for designers of memory controllers, Leinwander said here Thursday (April 28) at the Denali Memcon Austin 2005 conference, organized by Denali Software, Inc. (Palo Alto, Calif.)
"There are too many buses, too many pins, too many interfaces," he argued. Intel's proposal is that a common execution bus be developed, based on the bus architecture now used for the low-power double-data-rate (LP-DDR) DRAMs. For the mass-storage subsystems, based either on NAND flash or the small one-inch disk drives, the Intel manager suggested that the industry standardize on the high-speed multi-media card (MMC) interface.