Portland, Ore. Growing carbon nanotubes on silicon chips could enable nanoscale transistors, but only if designers can specify exactly where the tiny devices grow. Now EEs at Cleveland's Case Western Reserve University have demonstrated how to grow nanotubes just precisely where you want them self-aligned across a wafer and self-welded during growth.
The Case Western EEs claim that their nanotube-enabled wafers merely need to be diced and the dice wire-bonded to a chip carrier. If that's indeed the case, the devices could be as reliable and cost-effective as current chips.
"The nanotubes grow where you want them to grow between two electrical posts," said Case Western EE and computer science professor Massood Tabib-Azar, who developed the technique with doctoral candidate Yan Xie.
Others have experimented with nanotube-based transistors; but because those devices grew in random locations on the substrate, researchers were limited to studying the structures wherever they happened to sprout. A few experimenters have harnessed electric fields to grow nanotubes in selected locations, but that technique is not scalable across a wafer.
"The self-welding is the really critical breakthrough," said Tabib-Azar. "They grow from one post and weld themselves to the other post. We used a surface treatment so that the carbon nanotube makes good mechanical contact."
The discovery was a happy accident. The initial intent of the experiment was to grow carbon nanotubes on a substrate that had been preseeded with iron nanoparticles. It was not until the researchers inspected their results with a scanning electron microscope that they realized they had cleared one of the hurdles standing in the way of carbon nanotube transistors: The tubes had grown only between the electrical posts.
"This was a surprise result, because we expected carbon nanotubes to grow everywhere there were iron nanoparticles, and there were iron nanoparticles many other places besides the posts," Tabib-Azar said.
Metallic nanoparticles serve as the catalyst that begins the process of growing a nanotube by plucking carbon atoms out of the gas flow and self-assembling them into a tube.
"We use very small metallic nanoparticles on these posts; our initial particles were about 100 angstroms [10 nanometers] or so," said Tabib-Azar. "The carbon gets dissolved inside of the iron nanoparticle until it reaches a saturation level, then it starts coming out in the form of a carbon nanotube."
Others have demonstrated the ability to grow individual carbon nanotubes on silicon substrates using an electrical field. In those experiments, the tubes grow wherever the field is applied. But the electrical-field technique cannot pattern a wafer ahead of time to determine where each nanotube will grow.
Tabib-Azar's process applies no electrical fields. "We locate the posts with lithography and deep reactive-ion etching," he said.
The posts were fabricated using a silicon-on-insulator process with 1 to 2 microns of silicon atop the insulator. Tabib-Azar does not yet know why the nanotubes grow only between the patterned posts, though he said the process does seem to be repeatable.
Meanwhile, he said he has "a couple of educated guesses" as to why the process works. "One is that the flow pattern of the gases we generate at the surface of the silicon wafer varies in the presence of these posts. We pattern the gas flow so that it is slow only around the posts. [Perhaps that is why] the nanotubes only grow there: Everywhere else, the flow is very fast, so it doesn't give the nanotubes time to grow."
Next, the researchers plan to build a nanotube-based sensor chip that would be ultrasensitive compared with existing chips. In particular, the group is working toward a more-sensitive ammonia and hydrochloric-acid sensor. The multiwalled carbon nanotubes being grown at Case Western show p-type conductivity and the current through them drops when exposed to ammonia or hydrochloric gases, making a gas sensor chip a logical first application.
The research was supported by the National Science Foundation, Semiconductor Research Corp. and the National Institute of Standards and Technology.