Portland, Ore. - Silicon nanowires could combine the best features of carbon nanotubes and amorphous silicon to overcome the liabilities of the circuit technologies being explored for large-area flexible substrates, research at Harvard University suggests. Potential applications for such substrates include disposable e-newspapers and wall-hanging displays.
Two of the candidates, amorphous silicon and organic semiconductors, are inherently slower than silicon. And while carbon nanotube transistors promise higher electron mobility than is possible with silicon, the tubes have not yet been demonstrated in an integrated circuit. The payoff of the Harvard work, the researchers maintain, will be a material with the electron mobility of nanotubes but with the low-temperature processing of organic semiconductors.
The team demonstrated a nanowire-based ring oscillator that operated at 12 MHz. While that is dismally slow by CMOS standards, it's still 20 times faster than today's integrated organic semiconductors. The researchers believe they can scale the approach to CMOS speeds in the future.
"We are not exploiting nano to build ultrasmall nanoscale devices; we are exploiting it to bring high-performance devices to an application area where the only competing materials are . . . low-performance or low-mobility materials," said Harvard professor Charles Lieber, who designed the ring oscillator chip with Harvard EE Donhee Ham. "If nanomaterials are going to be useful, then you have to start putting them into small circuits. We focused on the ring oscillator as a test structure [because it's a structure that] that people are very familiar with."
Lieber and Ham were assisted by Harvard EE David Ricketts and by Robin Friedman and Michael McAlpine of the university's chemistry department.
Lieber began experimenting with carbon nanotubes in 1996 but became disillusioned at the difficulty of arraying them on a substrate. By switching to silicon nanowires, Lieber believes, the best of both worlds can be achieved. High-temperature silicon processing creates the high-speed nanowires, but then low-temperature chemistry is used to pattern them onto an inexpensive plastic substrate. There they are interconnected and bonded with inexpensive processes similar to those used for organic semiconductors. The result: the speed of silicon, but the low cost of plastic.
"We make the nanowires at a relatively high temperature, similar to what people are doing with thin-film CVD [chemical-vapor deposition] growth of silicon or germanium," said Lieber. "We are working at around 350 degrees C to 400 degrees C, using a nucleating catalyst. But we can put these devices on any kind of substrate. It doesn't have to be silicon."
Step one, then, is to use CVD to grow single-crystal nanowires with silicon or germanium, or even with more-exotic materials, while controlling their diameters down to just a couple of nanometers' tolerance. Step two suspends the nanowires in a liquid and then applies room-temperature photolithography and metallization processes similar to those used for organic semiconductors.
Lieber offered an analogy: "If you put a stick in a stream, it aligns with the flow [direction]." In the Harvard process, he said, "we just line the nanowires up all over the substrate, and then we come down with several steps of photolithography-which we initially pattern by subtracting nanowires from regions of the substrate where we don't want them. Then we put on the source and drain electrodes, then the gate dielectric, and finally we do the interconnect, using photolithography and metallization."
Prepatterning the substrate with arrays of nanowires is similar to using a resist, except that the structures can be spun onto almost any surface.
"The key is that we are depositing these nanowires using a fluid, low-temperature process," Lieber said. The contact metallization, he said, "can be done either with or without the need for annealing"-and even when annealing is used, it's done at very low temperatures.
The nanowires themselves were fabricated from the same materials used for today's high-performance CMOS transistors, holding out the promise that nanowire circuitry will eventually run at speeds similar to CMOS.
The pursuit is worth the effort because "you end up with single-crystal silicon nanowires that have mobilities and device properties comparable to the best that can be made at Intel," said Lieber. "Currently, we are using silicon germanium for the same reason that other people want to use silicon-germanium: for its very high [electron] mobility."
In circuits, the nanowires perform the same function as today's high-performance silicon transistors. While researchers have struggled in the past to attach electrodes to tiny carbon nanotubes to build circuits, the Harvard approach is said to overcome that problem via an architecture that uses redundant arrays of nanowires.
"We are not trying to get a one-to-one registry of source-drain electrodes; we just put down a regular pitch of electrodes, registered to the average position of the nanowires, and use, say, five nanowires bridging the source and drain, plus or minus one nanowire, which you can adjust based on its average spacing," said Lieber. "It's a way of getting around the problem of exact placement of deterministic wiring."
In the test circuit, Lieber's team wired up a series of three inverters, looping the output of the last inverter back into the input of the first one to create a classic ring oscillator. The current device uses PMOS transistors, but Lieber has also demonstrated nanowire NMOS transistors.
"These devices look very much like what is being fabricated as silicon-on-insulator at Intel," Lieber said. But whereas Intel makes "wire-like structures," he said, the Harvard team makes "perfect wires, where one end is the source and one end is the drain, and then you have a gate."
To that point, Lieber said, his structure "looks like a very conventional transistor. But then we put two of these together, running one at a constant load, and that gives you this PMOS inverter structure. Then you wire them up to make the ring oscillator."
In the demonstration, Lieber's group showed that an entire chip could be arrayed with nanowires, so that hundreds of nanoscale ring oscillators could be reproduced across a wafer-as would be necessary if practical commercial chips are to be fabricated in accordance with Lieber's method. "We are getting reasonable reproducibility in terms of dielectric thickness, channel length and so on," he said.
The experimental circuit's slow performance relative to CMOS reflects its status as an unoptomized prototype, Lieber said. Further, he said, a low-k dielectric was chosen for the gate oxide, masking the true speed possible with the process.
"Right now our channel lengths are 2 microns, which is very long, and we have really lousy dielectrics," he said. "We are working on going down to the submicron scale and implementing high-k dielectrics. Our estimate is that by using these scaling tricks, we can get from RF to microwave frequencies."
The current ring oscillator uses nanowires that are 20 nanometers in diameter, but the group has already demonstrated much smaller nanowires, down to 3 nm in diameter. The group has also shown that different formulations of nanowires can essentially be "dialed in" using simulation tools. "We can model it, then grow it," said Lieber.
This should make it possible to upgrade designs just by substituting faster nanowires. The group is experimenting with many formulations for the wires to demonstrate how speed performance might be bumped up in the future without the need for a geometry shrink.
Next, the group wants to demonstrate more-complicated circuits that would perform some simple digital or sensing function. By demonstrating the ability to integrate entire application circuits, Lieber hopes to attract an industrial partner to commit to trying out the process in commercial chips.
"We hope to build a shift register, or other slightly more-complicated circuit, and continue to scale up, bringing this work together with other work we are doing to build entire rudimentary computing systems."
Lieber has demonstrated a nanowire-based address decoder and he is collaborating with California Institute of Technology professor Andre DeHon to create an FPGA based on prepatterned areas of nanowire-based devices.