Santa Cruz, Calif. Paul Cunningham and Steev Wilcox, both recent PhD graduates from the University of Cambridge, England, didn't look for jobs after college. Instead they launched Azuro Inc., an EDA startup that's rolling out a power clock implementation solution this week.
Three years after its founding, U.S.-based Azuro has 27 employees, $4 million in venture capital, 10 patents pending and a product called PowerCentric in use at Broadcom Corp. and now ready for production shipment. The company is targeting the wireless market with PowerCentric, which combines clock tree gating with clock tree balancing and replaces existing clock tree synthesis solutions.
"Most EDA startups are either spin-offs from universities or are people leaving existing corporations, but we really did start with a clean sheet here," said Cunningham, Azuro's CEO. Azuro's technology is not based on research from Cambridge. Cunningham said he got the idea to form a company based on power optimization after serving an internship with computer science guru Ivan Sutherland at Sun Microsystems Inc. Cunningham was designing high-performance micro-pipelined switching fabrics, and he saw firsthand how pervasive the power problem was.
Cunningham returned to Cambridge to finish his PhD and brought Wilcox, now Azuro's chief architect, into the picture. "He's able to take the most abstract idea and immediately turn it into an algorithm," Cunningham said. "I was the kind of guy always floating around with concepts and ideas."
Today, Azuro is located in Mountain View, Calif., and so is Cunningham. Seventeen of its 27 employees are at the R&D center in Cambridge, but there was no doubt Azuro needed to be located in Silicon Valley, Cunningham said. It recently raised $4 million in venture funding from Benchmark Capital.
Existing EDA companies and startups alike are addressing the IC power-management problem. But Azuro's approach is different, Cunningham said, because it intends to focus on one problem at a time and quantify the results. "Existing flows have so much inertia that they're not keeping pace," he said. "They're trying to throw everything in and saying that we do it all. There's no thought given to how well they're solving any particular problem."
In addition to tackling a specific problem clock-related power Azuro has targeted a specific market: next-generation wireless devices. "We think it's important for a company to identify who it's going after from a customer standpoint," Cunningham said. "Yes, power is pervasive across the semiconductor industry, but the wireless market is really driving the EDA industry."
Azuro's is indeed a fresh approach, said Gary Smith, chief EDA analyst at Gartner Dataquest. "What they are doing is putting together power reduction technology, which is a lot different than just another clock tree or synthesis company," Smith said.
Clock power is Azuro's initial target, Cunningham said, because the clock and registers combined can consume up to 80 percent of a chip's dynamic power. Today, most engineers implement clock gating which turns portions of the clock network on and off at the register-transfer level. But the actual clock network is not implemented, or synthesized, until after placement, because a designer needs to know where the registers are located first.
Because these steps are disconnected, designers aren't able to find the best clock-gating topologies and they can't optimize the clock gating and the buffering together, Cunningham said. "PowerCentric is a complete clean-sheet rewrite of clock tree gating and clock tree buffering in one engine," he said. "At the end of the day, we can find a better solution than anybody else."
Azuro thus makes the bold claim that it can replace the clock tree synthesis offered by RTL-to-GDSII implementation providers. Using standard file formats, PowerCentric runs after physical synthesis and before final routing, producing a balanced, gated clock tree that meets timing with no sacrifice in area, said Cunningham.
PowerCentric offers "gated synthesis," which offers automatic clock gate creation from a gate-level netlist; intelligent clock tree synthesis, which simultaneously optimizes clock gating and clock buffers; and SASim, a vectorless simulation tool that reports average-case power estimation. The $150,000 tool supports as many as 750,000 cell instances on a 32-bit machine, Azuro said.