SAN FRANCISCO The cost-per-function of ICs will continue to decline long after Moore's Law is obsolete, thanks to various future design and fabrication innovations, Mentor Graphics Corp. Chairman and CEO Walden Rhines said Tuesday (May 17).
Delivering a keynote address at In-Stat's Spring Processor Forum in San Jose, Calif., Rhines said that Moore's Law is not a law at all but an empirical observation. He characterized a law as something absolute and presented several contradictory public statements by Intel co-founder Gordon Moore, including his 1975 revision increasing from one year to two the amount of time in which the number of transistors on a chip would double, as evidence that the terms of Moore's Law have been in flux over the years.
"It seems like a law shouldn't be so variable," Rhines said.
Moore's Law has performed very well over the past 40 years, Rhines argued, because it is based on a fundamental law of naturethe learning curve. Rhines said cost-per- unit of anything decreases by a fixed percent every time the total cumulative volume doubles, adding that this applies to all products over centuries when measured in constant currency. He said the law of the learning curve has been used to successfully predict future costs in a number of industries, including the aircraft and semiconductor industriesespecially with regard to DRAM.
"Even the price of Japanese beer follows a learning curve," Rhines said.
According to Rhines, Moore's Law has been an accurate predictor for the semiconductor industry because the cumulative number of transistors produced increases exponentially with time and, to date, almost all cost reduction has been achieved from shrinking feature sizes and growing wafer diameter. But as the industry approaches a time when it will no longer be physically possible or economically feasible to double the number of transistors on a chip every two years, the methods for achieving higher quality and lower costs will change.
"As Moore's Law assumptions become less valid, something will have to change," Rhines said. "And that is the way that we achieve a lower cost going forward."
Rhines highlighted several emerging and improving technologies that he said would continue to reduce design and manufacturing costs, enabling the cost-per-function of ICs to continue to decline after the fall of Moore's Law.
Among the areas that Rhines highlighted as future areas of cost reduction was verification, which he said has become a major bottleneck, accounting for as much of half of a designer's time.
"The design cost is going up because so much of your time is spent verifying what you have designed," Rhines said. "Design engineers are becoming verification engineers."
But most verification being done today is redundant, Rhines said, adding that the emergence of assertion-based design would dramatically improve verification quality and reduce effort.
Among the other improvements Rhines predicted would be areas of cost reduction were innovative assembly and packaging of multiple-chip modules, power-aware design rules, design-for-manufacturing (DFM) improvements, lithography-friendly tools to enable designers to analyze the effects of manufacturing variability and the integration of physical verification and test to enhance debugging and improve yields.
"As Moore's law becomes less and less a predictor," Rhines said, "we'll still have the learning curve that will tell us what needs to happen beyond just shrinking the design rules."