SAN FRANCISCO Power reduction has become the No. 1 design concern, according to Golden Gate Technology Inc. CEO Dennis Heller, who said his company's new software products can reduce IC power consumption by up to 25 percent.
The products, Power Optimize Gold and Power Plan Gold, work with existing place and route flows from Cadence Design Systems Inc., Synopsys Inc. and Magma Design Automation Inc.
According to Golden Gate Technology (San Jose, Calif.), Power Optimize Gold reduces leakage and switching power while simultaneously meeting constraints for timing, signal integrity and electromigration. Power Plan Gold creates architectural multi-voltage-island designs by automatically creating complex power grids, the company said.
Power consumption has always been a major concern, Heller said, but it has become the primary design concern across several classes of chips, including cell phone chips, where power consumption impacts battery life, consumer electronics chips that need to stay within power limits to remain in inexpensive plastic packages and networking chips, which are destined for infrastructures that have a limited cooling capacity. While designers are placing heightened emphasis on power consumption, he added, they are not willing to sacrifice timing, which had previously been the top concern.
"From now on, it's not just a matter of how capable a chip is," Heller said, "but how much capability you can package on a chip and still have acceptable power consumption."
Heller said a number of software companies have recognized that power consumption has become the top design priority. But while most other companies are doing power analysis, he said, giving customers the capability to measure the power consumption of their devices, only Golden Gate Technology is actually providing the ability to reduce the power consumption of a design.
Golden Gate Technology's software concentrates on reducing the power consumption of wires, since, it says, wires burn the majority of power on sub-100 nanometer chipsfive times more than transistors at the 90 nm node. The company's software uses a patent-pending optimization technology called WiresFirst to minimize the total capacitance on critical clock and signal nets through route optimization and isolation techniques which reduce power without impacting chip timing, signal integrity, or electromigration.
A key selling feature, according to Heller, is that Power Optimize Gold and Power Plan Gold fit into customers' existing design flows. "Both products work with existing design flows," Heller said. "We are not asking customer to replace of supplant their existing design flow. We are simply asking them to augment it."
Power Optimize Gold and Power Plan Gold are shipping now for Solaris and Linux. Pricing for time-based licenses starts at $115,000 for Power Plan Gold and $395,000 for Power Optimized Gold.