With SRAM, DRAM and flash high-stepping down the road map for both standalone and embedded designs, any competing memory chip technology faces an uphill battle. Nevertheless, other types of memory in various stages of development are rumbling offstage.
Ferroelectric random-access memory, for example, has entered mass production at Ramtron International Corp. and is close to commercialization elsewhere. Beyond FRAM comes a bewildering array of alternatives, some still in basic research and all aiming to shrink design rules toward the angstrom scale (an angstrom is one-tenth of a nanometer). Among the contenders are magnetic tunnel-junction RAM (MRAM), phase-change RAM (PRAM), nanowire and nanotube designs, and molecular memories.
For any of these, however, gaining traction will probably mean following in the footsteps of Ramtron and finding a niche in which to flourish while sustaining the long-term research required to someday catch up to DRAM and flash.
"If you look forward five years, there is time for more innovative or novel or prospectively promising technologies to demonstrate their capabilities and start to make some appearances in the mainstream markets," said Lane Mason, a staff analyst at Denali Software Inc., a Palo Alto, Calif., supplier of electronic design automation software and intellectual-property cores for memory architectures. "Today, FRAMs and the chalcogenide memory technology [PRAMs] are being used in certain applications, but they are very much niche and off the edge of the mainstream where silicon is used right now."
For any of them to succeed, Mason said, "they will have to find their way in their own markets. It's just wishful thinking that they are going to displace silicon this decade."
FRAM makes use of ferroelectric crystal materials usually oxides that can permanently switch the electric dipole moment (a measure of the degree of polarity of a polar molecule) without an external electric field. Hence, they are nonvolatile. Bulk ferroelectric materials spontaneously form into nanoscale dipoles that can be electrically switched in the lab from within domains just a few nanometers in diameter called quantum dots. FRAMs have been researched by Celis Semiconductor, Hynix, Macronix, Infineon, Ramtron, Samsung, Sanyo, Texas Instruments and Toshiba.
Theoretically, FRAMs have the potential to create incredible densities using quantum dots as cells. For instance, University of Arkansas professors Huaxiang Fu and Laurent Bellaiche recently reported simulation results showing that 5-nanometer ferroelectric quantum dots created small magnetic vortexes that could be "unraveled" to represent bits.
From lab to production line
"We are in mass production, we are shipping millions of units per quarter, but our appeal is to applications where you need something other than what you get from flash," said Mike Alwais, vice president at Ramtron (Colorado Springs, Colo.). "The manufacturing challenges of these new technologies that is what gets underreported. It's harder than it looks."
To survive, Ramtron found a market niche to sustain its R&D efforts. Today, the bulk of its shipments are direct replacements for use in data acquisition devices, such as meters, that now use SRAMs equipped with battery backup. Ramtron's latest chip is a 1-Mbit FRAM that's a plug-in replacement for a like-sized SRAM. The device has already been scaled down to the 0.13-micron node, with samples due this year; 90-nm parts have been designed, with 65 nm on the drawing board.
The company still has high hopes for the long-term success of FRAM, even against flash. "At the advanced nodes, 65 nm and beyond, our customers believe that FRAM has a better chance to scale than flash, because we don't require very thin oxides or high voltages," said Alwais.
Texas Instruments Inc. has licensed FRAM from Ramtron to reduce the cost of nonvolatile embedded memory compared with flash. For instance, FRAM requires that only two extra masks be added to an embedded chip, against as many as nine for embedded flash. Currently, Ramtron uses Fujitsu as its production foundry, but TI will soon make Ramtron FRAM technology too. The partners are co-developing a standalone 4-Mbit FRAM with 0.13-micron design rules that TI will use as a core for its DSPs and Ramtron will sell as a separate chip. Samples are due later this year.
"Embedded FRAM makes a lot of sense where low-power nonvolatile memory is required," said Ted Moise, FRAM program manager at Texas Instruments (Dallas). "It embeds in a much more straightforward manner and has better performance than any of the alternatives we see out there."
According to TI, the problem with embedded flash is the overhead circuitry necessary to drive the 18-volt programming pulses for writing and erasing bit cells.
"Flash has a very small cell size, but embedding flash doesn't make sense unless you are going to embed a lot of memory," Moise said. "That's because of all the overhead circuitry you need with flash to handle the high voltage. If you only need a few megabits of memory on your embedded chip, like a microcontroller, it doesn't make sense to use flash with all its overhead."
TI expects to begin sampling 4-Mbit standalone FRAM chips to Ramtron later this year, but the company does not expect to add FRAM to any of its embedded chips until late 2006 or 2007.
The next-best bet behind FRAM is MRAM, which stores a bit in a magnetic-tunnel junction, a sandwich structure that includes a pinned magnetic layer, an oxide tunnel barrier and a free magnetic layer. Two metal electrodes switch the free layer between two magnetic-polarization states. Reading is accomplished by sensing a change in resistance.
MRAMs have been researched for many years at Altis Semiconductor (an alliance of IBM and Infineon), Freescale, NEC/Toshiba, Samsung and Sony. Several of these companies have announced successful experimental chips as large as 128 kbits, while Cypress Semiconductor Corp. (San Jose, Calif.) reported densities up to 256 kbits. Cypress, however, recently said it will divest itself of Silicon Magnetic Systems, the subsidiary founded to commercialize MRAMs (see www.eet.com/article/showArticle.jhtml?articleID=60400459).
Also scaling back is NVE Corp. (Eden Prairie, Minn.). NVE recently said it had discontinued its efforts to sell standalone MRAM devices (visit www.eetimes.com/showArticle.jhtml?articleID=160904080). Now, it will sell only its intellectual property for a 256-kbit MRAM design "MRAM has fast read/write as well as high density, and you can get an MRAM cell in many manufacturers' libraries today," said Denali's Mason. "The problem with MRAM has been lifetime, durability and reproducibility."
Mason said he was "very disappointed recently to see Cypress drop out" of the MRAM race. For MRAMs and PRAMs, he said, a lot of the knowledge the industry has accumulated about silicon "is transferable, so it's not necessarily a David-and-Goliath thing. But still, it's pretty hard to imagine MRAM displacing the road map's momentum and establishing a market position alongside DRAM or flash."
Freescale Semiconductor Inc. is currently sampling a 4-Mbit MRAM that it claims is meeting all its expectations and may be chosen by a customer as early as 2006. At the upcoming VLSI Symposium, to be held in Kyoto, Japan, June 14-18, Freescale will show how to scale down its MRAM to the 90-nm node, said Saied Tehrani, director of MRAM technology at the Austin, Texas, company.
"We are sampling now, and everything on the spec sheet is working fine," said Tehrani. "We have a 35-nanosecond read/write cycle and unlimited endurance. We are faster than flash, but not as dense. We are easier to integrate only five extra masks at the end of the process so you don't have to redesign at the transistor level like you have to do with flash. All the other core technologies in your design remain the same and function in the same way."
Freescale is now qualifying its 4-Mbit MRAM sample, which was run on a standard CMOS line, to ensure that it meets long-term quality goals "so that we don't have failures in the field," said Tehrani. "We are also designing a magnetic shield to put on top of the die so that MRAM cannot be erased by an external magnetic field. Then we are coming up with a cost point that is competitive."
In the long haul, Freescale thinks MRAM can challenge flash at the advanced nodes. "We are going to demonstrate our first chip at the 90-nm node at the VLSI Symposium, and we will also show there that MRAM can scale more easily than flash," Tehrani said. "Our data will show that we can scale the bit cells to the 65-nm node and probably beyond."
The biggest obstacle facing MRAM, according to Freescale, is that it takes a lot of current to switch the magnetic polarization of a cell. Thus, overly large driver transistors are necessary for writing. "One of our remaining challenges is to scale down the driver transistors," said Tehrani.
Technologically similar to writable DVDs, phase-changing memory also known as ovonic or chalcogenide memory is probably just behind MRAM in terms of commercial potential. Several electronics giants have channeled R&D funds into PRAM technologies, including Elpida Memory, Intel, Philips Research, Samsung and STMicroelectronics.
As in writable DVDs, the state of a nonvolatile phase-change memory cell is converted from amorphous to crystalline. DVDs use a laser to heat the material to switch it between its amorphous and crystalline phases and to read out the resultant change in its reflectivity. In chips, an electric current does the job: By heating a thin film of doped chalcogenide, the current switches it between phases the resistive amorphous state, called the reset state, and the conductive crystalline state, or the set state.
PRAMs usually use chalcogenide doped with antimony, germanium or telluride. The cell is read out electrically by sensing the change in electrical resistance. Phase-change materials for nonvolatile memory have been under investigation at such companies as Intel, STMicroelectronics and Elpida, all of which have licensed technology from Ovonyx Inc. (Santa Clara, Calif.), which uses chalcogenide alloys of antimony telluride and germanium telluride (see www.eetimes.com/news/semi/technology/showArticle.jhtml?articleID=159900731).
So far, PRAM yields and reliability have been low compared with FRAMs and MRAMs; but with the giant R&D budgets at Samsung, Intel and Philips targeting the problem, solutions will likely be found. Samsung Electronics Co. Ltd. (Seoul, South Korea) has already demonstrated a "differential" PRAM architecture that ups reliability by representing each bit by a combination of one crystalline and one amorphous cell. Macronix International Co. Ltd., in Taiwan, has also shown both PRAMs and related resistive RAMs (RRAMs), while Germany's Infineon Technologies AG has shown experimental organic RRAMs (www.techweb.com/wire/26802834).
Beyond the end of the road map beckon subnanoscale feature sizes measured in angstroms. Candidates in this realm include transistor channels made from nanowires, memories with grown-in-place nanotube transistor channels, nanoscale microelectromechnical-systems (MEMS) and memories with single-molecule (angstrom-scale) transistor cells.
Prepatterning wafers with ultrasmall, nanoscale features such as with arrays of nanowires 2 nm wide to serve as transistor channels has already been demonstrated. Harvard University professor Charles Lieber recently demonstrated a prepatterned chip and explained how his technique could sidestep the road map's shrinkage problems (www.eetimes.com/showArticle.jhtml?articleID=162800186).
Instead of endlessly shrinking silicon design rules to yield more speed, Lieber believes, a better bet is to leave the design rules constant and gain speed by designing better nanowires with which to prepattern wafers.
A former nanotube researcher, Lieber is now championing silicon nanowires: They have the electron mobility of nanotubes but can be processed at both high and low temperatures, and they don't require an expensive single-crystal silicon substrate. The nanowire-based ring oscillator that Lieber demonstrated was 20 times faster than today's integrated organic semiconductors and promises to scale up to CMOS speeds but on inexpensive plastic substrates.
Another potential breakthrough was reported this year for using nanotubes as transistor channels. Case Western professor Massood Tabib-Azar demonstrated how to grow carbon nanotubes on silicon chips between photolithographically defined electrodes. The nanotubes were self-aligned across the wafer and self-welded during growth, suggesting that nanoscale channel-less transistors could be fabricated photolithographically, after which the tiny nanotube channels could be grown using chemical-vapor deposition. Such nanotube-enabled wafers could run on standard CMOS lines, Tabib-Azar said (www.eetimes.com/showArticle.jhtml?articleID=162100187).
IBM Corp. and many other organizations have previously experimented with nanotube and nanowire transistors, showing them to have much higher electron mobility than even the most advanced silicon transistor designs. IBM has also shown nanotube transistors only 10 atoms wide, or 500 times smaller than current silicon transistors.
Unfortunately, without a method of easily attaching electrodes to the 15-angstrom-diameter nanotubes, IBM could only test them one at a time with an atomic-force microscope. With new technologies to prepattern wafers or to grow nanotubes in place, however, it should be possible to use nanotubes and nanowires to extend traditional silicon's road map down to the angstrom level, researchers believe. If Harvard's Lieber is right, the road map can be extended even further without endless shrinkage by brewing up ever-higher-mobility nanowires and nanotube formulations.
IBM has also demonstrated mechanisms using MEMS-based memories that change a nanoscale mechanical state to store a bit. For instance, IBM developed a prototype terabit memory that stores a trillion bits of data in a square inch. The Millipede nonvolatile memory precisely moved a silicon substrate coated with a thin-film polymer beneath an array of 1,024 parallel-activated 20-nm-diameter read/write heads, which were also etched from silicon. A bit was marked by heating a head to melt the polymer beneath it.
Nobel laureate Gerd Beinnig, who worked on the Millipede project, predicted that IBM's nanoscale approach to mechanical memory was good for another thousandfold increase in data storage density, to yield 15-Gbyte chips within the next decade (www.eet.com/story/OEG20020611S0018).
At even smaller scales, some research labs are pursuing molecular memories that use individual atoms in angstrom-scale transistor cells. ZettaCore Inc., for instance, is a Denver startup specializing in molecular memories invented by professor Jonathan Lindsey at North Carolina State University (Raleigh).
Lindsey recently demonstrated that molecular memories have charge-retention times several orders of magnitude longer than DRAMs' (minutes vs. milliseconds), that individual molecules can withstand the extreme temperatures of silicon fabrication (400°C) and that molecular memories can undergo as many as a trillion read-write cycles (www.eetimes.com/story/OEG20031222S0027). ZettaCore is currently engineering a catalog of electronic molecules that it plans to offer to the semiconductor industry as components in future angstrom-scale memory designs.