SAN FRANCISCO Cadence Design Systems Inc. has extended the IR drop analysis capability of its Voltage Storm power analysis tool. The capability, known as PowerMeter, is designed to enable signoff-quality dynamic power rail analysis and power calculation.
According to Cadence (San Jose, Calif.), PowerMeter uses dynamic power calculation algorithms to enable design teams to accurately calculate and distribute leakage, internal and switching power consumption for every instance of a design.
Pete McCrorie, Cadence's design-for-manufacture (DFM) technical marketing director, said the PowerMeter functionality addresses a significant issue facing designers, who are finding that the tight dimensions of leading-edge process technologies have no tolerance for IR drop. "With newer technologies, you simply cannot design to a given percentage of given IR drop," McCrorie said.
Cadence said that PowerMeter, when used with VoltageStorm's dynamic gate (DG) option, calculates the distributed dynamic power used to drive the dynamic rail analysis of a design, which determines the impact of voltage drop transients on the power and ground rails of a design. The information gained can help designers optimize power routing widths and determine the size and location of de-coupling capacitors used to tame IR drop transients, the company said.
IR drop is a voltage drop caused by electrical resistance. According to Cadence, static power rail verification methodologies must be complemented with dynamic analysis to consistently achieve working silicon at 130 nanometers and below. The company said that designers could control significant IR drop transients on the power rails by adding de-coupling capacitance, but that this process must be carefully optimized to control power consumption.
Cadence said VoltageStorm DG uses PowerMeter to highlight areas of high simultaneous switching that can cause power rail failure. PowerMeter is designed to calculate power waveforms for each of the instances within a cell-based design, enabling engineers to observe large IR drop spikes and adjust on-chip de-coupling capacitors to address them.
"Design teams want to know how much de-coupling they need and where to put it," McCrorie said. "But they are trying to strike a balance, knowing that if they add too many de-coupling capacitors, a chip will not work,"
Li-Siang Lee, physical design manager at Cortina Design Systems, said in a statement that his company has used PowerMeter to help understand the effectiveness of its power rail de-coupling capacitors. "VoltageStorm DG's vectorless approach using PowerMeter clearly showed us where power was being consumed, and where we could optimize our capacitance size and locations," Lee said. "We are now confident that IR drop transients will not be a cause of silicon failure for our latest tapeout."
PowerMeter is available now as a standard capability on the VoltageStorm power analysis product. List price for the VoltageStorm PE product is $170,000, with VoltageStorm DG available as an option for an additional $80,000.